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Searched refs:ddrphy_cfg (Results 1 – 20 of 20) sorted by relevance

/u-boot/board/gateworks/venice/
A Dlpddr4_timing.c1980 .ddrphy_cfg = lpddr4_ddrphy_cfg_1gb,
2496 .ddrphy_cfg = lpddr4_ddrphy_cfg_4gb,
/u-boot/drivers/ddr/imx/imx8m/
A Dhelper.c160 saved_timing->ddrphy_cfg = cfg; in dram_config_save()
162 cfg->reg = timing_info->ddrphy_cfg[i].reg; in dram_config_save()
163 cfg->val = timing_info->ddrphy_cfg[i].val; in dram_config_save()
A Dddrphy_train.c23 dram_cfg = dram_timing->ddrphy_cfg; in ddr_cfg_phy()
/u-boot/board/google/imx8mq_phanbell/
A Dlpddr4_timing_1g.c1722 .ddrphy_cfg = ddr_ddrphy_cfg,
/u-boot/board/technexion/pico-imx8mq/
A Dlpddr4_timing_1gb.c1724 .ddrphy_cfg = ddr_ddrphy_cfg,
A Dlpddr4_timing_2gb.c1724 .ddrphy_cfg = ddr_ddrphy_cfg,
A Dlpddr4_timing_3gb.c1724 .ddrphy_cfg = ddr_ddrphy_cfg,
A Dlpddr4_timing_4gb.c1724 .ddrphy_cfg = ddr_ddrphy_cfg,
/u-boot/board/beacon/imx8mn/
A Dlpddr4_2g_timing.c1431 .ddrphy_cfg = ddr_ddrphy_cfg,
A Dlpddr4_timing.c1424 .ddrphy_cfg = ddr_ddrphy_cfg,
/u-boot/board/phytec/phycore_imx8mm/
A Dlpddr4_timing.c1837 .ddrphy_cfg = ddr_ddrphy_cfg,
/u-boot/board/phytec/phycore_imx8mp/
A Dlpddr4_timing.c1840 .ddrphy_cfg = ddr_ddrphy_cfg,
/u-boot/board/freescale/imx8mn_evk/
A Dddr4_timing.c1204 .ddrphy_cfg = ddr_ddrphy_cfg,
/u-boot/board/freescale/imx8mp_evk/
A Dlpddr4_timing.c1839 .ddrphy_cfg = ddr_ddrphy_cfg,
/u-boot/board/toradex/verdin-imx8mm/
A Dlpddr4_timing.c1841 .ddrphy_cfg = ddr_ddrphy_cfg,
/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c1972 .ddrphy_cfg = lpddr4_ddrphy_cfg,
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c1972 .ddrphy_cfg = lpddr4_ddrphy_cfg,
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c1180 .ddrphy_cfg = lpddr4_ddrphy_cfg,
A Dlpddr4_timing.c1317 .ddrphy_cfg = lpddr4_ddrphy_cfg,
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h690 struct dram_cfg_param *ddrphy_cfg; member

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