| /u-boot/drivers/i2c/ |
| A D | i2c-gpio.c | 92 udelay(delay); in i2c_gpio_write_bit()
94 udelay(delay); in i2c_gpio_write_bit()
104 udelay(delay); in i2c_gpio_read_bit()
106 udelay(delay); in i2c_gpio_read_bit()
116 udelay(delay); in i2c_gpio_send_start()
118 udelay(delay); in i2c_gpio_send_start()
120 udelay(delay); in i2c_gpio_send_start()
122 udelay(delay); in i2c_gpio_send_start()
129 udelay(delay); in i2c_gpio_send_stop()
131 udelay(delay); in i2c_gpio_send_stop()
[all …]
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| A D | i2c-versatile.c | 27 u32 delay; member
33 udelay(priv->delay); in versatile_sda_set()
40 udelay(priv->delay); in versatile_sda_get()
47 udelay(priv->delay); in versatile_scl_set()
54 udelay(priv->delay); in versatile_scl_get()
61 udelay(priv->delay); in versatile_i2c_start()
82 udelay(priv->delay); in versatile_i2c_read_bit()
92 udelay(priv->delay); in versatile_i2c_write_bit()
242 priv->delay = 1000000 / (speed << 2); in versatile_i2c_set_bus_speed()
254 priv->delay = 25; /* 25us * 4 = 100kHz */ in versatile_i2c_probe()
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| A D | nx_i2c.c | 127 uint delay = 0; in nx_i2c_set_sda_delay() local
136 delay = DIV_ROUND_UP(bus->sda_delay, t_pclk); in nx_i2c_set_sda_delay()
138 delay = DIV_ROUND_UP(delay, SDADLY_CLKSTEP); in nx_i2c_set_sda_delay()
140 if (delay > SDADLY_MAX) { in nx_i2c_set_sda_delay()
141 delay = SDADLY_MAX; in nx_i2c_set_sda_delay()
143 __func__, bus->sda_delay, t_pclk * delay * SDADLY_CLKSTEP, in nx_i2c_set_sda_delay()
147 __func__, bus->sda_delay, t_pclk * delay * SDADLY_CLKSTEP, in nx_i2c_set_sda_delay()
151 delay |= I2CLC_FILTER; in nx_i2c_set_sda_delay()
153 delay = 0; in nx_i2c_set_sda_delay()
157 delay &= 0x7; in nx_i2c_set_sda_delay()
[all …]
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| /u-boot/drivers/net/phy/ |
| A D | miiphybb.c | 180 bus->delay(bus); in miiphy_pre()
182 bus->delay(bus); in miiphy_pre()
185 bus->delay(bus); in miiphy_pre()
187 bus->delay(bus); in miiphy_pre()
190 bus->delay(bus); in miiphy_pre()
192 bus->delay(bus); in miiphy_pre()
195 bus->delay(bus); in miiphy_pre()
197 bus->delay(bus); in miiphy_pre()
252 bus->delay(bus); in bb_miiphy_read()
254 bus->delay(bus); in bb_miiphy_read()
[all …]
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| /u-boot/doc/device-tree-bindings/video/ |
| A D | intel-gma.txt | 15 - intel,panel-power-cycle-delay : T4 time sequence (6 = 500ms)
18 - intel,panel-power-up-delay : T1+T2 time sequence
19 - intel,panel-power-down-delay : T3 time sequence
20 - intel,panel-power-backlight-on-delay : T5 time sequence
21 - intel,panel-power-backlight-off-delay : Tx time sequence
33 intel,panel-power-cycle-delay = <6>;
34 intel,panel-power-up-delay = <2000>;
35 intel,panel-power-down-delay = <500>;
36 intel,panel-power-backlight-on-delay = <2000>;
37 intel,panel-power-backlight-off-delay = <2000>;
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| A D | tegra20-dc.txt | 27 * delay before asserting panel_vdd
28 * delay between panel_vdd-rise and data-rise
29 * delay between data-rise and backlight_vdd-rise
30 * delay between backlight_vdd and pwm-rise
31 * delay between pwm-rise and backlight_en-rise
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| /u-boot/arch/arm/dts/ |
| A D | k3-am654-industrial-thermal.dtsi | 6 polling-delay-passive = <250>; /* milliseconds */
7 polling-delay = <500>; /* milliseconds */
20 polling-delay-passive = <250>; /* milliseconds */
21 polling-delay = <500>; /* milliseconds */
34 polling-delay-passive = <250>; /* milliseconds */
35 polling-delay = <500>; /* milliseconds */
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| A D | exynos5422-odroidxu3.dts | 48 regulator-ramp-delay = <12000>;
56 regulator-ramp-delay = <12000>;
63 regulator-ramp-delay = <12000>;
70 regulator-ramp-delay = <12000>;
78 regulator-ramp-delay = <12000>;
86 regulator-ramp-delay = <12000>;
94 regulator-ramp-delay = <12000>;
102 regulator-ramp-delay = <12000>;
110 regulator-ramp-delay = <12000>;
118 regulator-ramp-delay = <12000>;
[all …]
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| A D | rk3288-thermal.dtsi | 11 polling-delay-passive = <1000>; /* milliseconds */
12 polling-delay = <5000>; /* milliseconds */
20 polling-delay-passive = <100>; /* milliseconds */
21 polling-delay = <5000>; /* milliseconds */
60 polling-delay-passive = <100>; /* milliseconds */
61 polling-delay = <5000>; /* milliseconds */
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| A D | sun50i-h6-orangepi-one-plus.dts | 20 startup-delay-us = <100000>;
33 allwinner,rx-delay-ps = <200>;
34 allwinner,tx-delay-ps = <200>;
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| A D | omap3-cpu-thermal.dtsi | 14 polling-delay-passive = <250>; /* milliseconds */
15 polling-delay = <1000>; /* milliseconds */
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| A D | sun50i-h6-pine-h64.dts | 68 startup-delay-us = <100000>;
78 startup-delay-us = <100000>;
106 allwinner,rx-delay-ps = <200>;
107 allwinner,tx-delay-ps = <200>;
187 regulator-enable-ramp-delay = <100000>;
247 regulator-ramp-delay = <2500>;
252 regulator-enable-ramp-delay = <32000>;
255 regulator-ramp-delay = <2500>;
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| /u-boot/cmd/ |
| A D | bootmenu.c | 89 if (menu->delay > 0) { in bootmenu_autoboot_loop()
94 while (menu->delay > 0) { in bootmenu_autoboot_loop()
102 menu->delay = -1; in bootmenu_autoboot_loop()
124 if (menu->delay < 0) in bootmenu_autoboot_loop()
127 --menu->delay; in bootmenu_autoboot_loop()
134 if (menu->delay == 0) in bootmenu_autoboot_loop()
223 if (menu->delay >= 0) { in bootmenu_choice_entry()
294 menu->delay = delay; in bootmenu_create()
438 if (delay == 0) { in bootmenu_show()
518 int delay = 10; in do_bootmenu() local
[all …]
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| A D | sleep.c | 17 ulong delay; in do_sleep() local
23 delay = simple_strtoul(argv[1], NULL, 10) * CONFIG_SYS_HZ; in do_sleep()
39 delay += mdelay; in do_sleep()
41 while (get_timer(start) < delay) { in do_sleep()
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| /u-boot/doc/device-tree-bindings/i2c/ |
| A D | generic-acpi.txt | 18 - reset-delay-ms : Delay after de-asserting reset, in ms
19 - reset-off-delay-ms : Delay after asserting reset (during power off)
20 - enable-delay-ms : Delay after asserting enable
21 - enable-off-delay-ms : Delay after de-asserting enable (during power off)
22 - stop-delay-ms : Delay after de-aserting stop
23 - stop-off-delay-ms : Delay after asserting stop (during power off)
38 reset-delay-ms = <20>;
40 enable-delay-ms = <1>;
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| A D | i2c-gpio.txt | 15 * i2c-gpio,delay-us = <5>;
16 The resulting transfer speed can be adjusted by setting the delay[us]
34 i2c-gpio,delay-us = <5>;
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| /u-boot/arch/arm/mach-zynq/ |
| A D | ps7_spl_init.c | 60 static unsigned long get_number_of_cycles_for_delay(unsigned long delay) in get_number_of_cycles_for_delay() argument
62 return (APU_FREQ / (2 * 1000)) * delay; in get_number_of_cycles_for_delay()
94 unsigned long delay; in ps7_config() local
130 delay = get_number_of_cycles_for_delay(mask); in ps7_config()
132 while (ioread(addr) < delay) in ps7_config()
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| /u-boot/arch/x86/lib/fsp2/ |
| A D | fsp_meminit.c | 68 int delay; in fsp_memory_init() local
83 delay = dev_read_u32_default(dev, "fspm,training-delay", 0); in fsp_memory_init()
89 delay = 0; in fsp_memory_init()
92 if (delay) in fsp_memory_init()
93 printf("SDRAM training (%d seconds)...", delay); in fsp_memory_init()
101 if (delay) in fsp_memory_init()
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| /u-boot/arch/mips/mach-mscc/include/mach/ |
| A D | common.h | 51 static inline void mscc_vcoreiii_nop_delay(int delay) in mscc_vcoreiii_nop_delay() argument
53 while (delay > 0) { in mscc_vcoreiii_nop_delay()
55 switch (delay) { in mscc_vcoreiii_nop_delay()
80 delay -= 8; in mscc_vcoreiii_nop_delay()
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| /u-boot/drivers/ddr/marvell/axp/ |
| A D | ddr3_read_leveling.c | 92 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
294 delay); in ddr3_read_leveling_sw()
414 delay = 0; in ddr3_read_leveling_single_cs_rl_mode()
474 delay, phase); in ddr3_read_leveling_single_cs_rl_mode()
526 delay++; in ddr3_read_leveling_single_cs_rl_mode()
540 delay = 0; in ddr3_read_leveling_single_cs_rl_mode()
562 delay = in ddr3_read_leveling_single_cs_rl_mode()
766 delay = 0; in ddr3_read_leveling_single_cs_window_mode()
877 delay; in ddr3_read_leveling_single_cs_window_mode()
949 delay++; in ddr3_read_leveling_single_cs_window_mode()
[all …]
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| A D | ddr3_write_leveling.c | 68 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
354 delay = in ddr3_wl_supplement()
363 phase, delay); in ddr3_wl_supplement()
370 delay = in ddr3_wl_supplement()
377 && (delay <= in ddr3_wl_supplement()
383 delay = 0x0; in ddr3_wl_supplement()
389 [D] = delay; in ddr3_wl_supplement()
394 phase, delay); in ddr3_wl_supplement()
1224 for (delay = 0; delay < MAX_DELAY; delay++) { in ddr3_write_leveling_single_cs()
1227 delay); in ddr3_write_leveling_single_cs()
[all …]
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| /u-boot/doc/device-tree-bindings/spi/ |
| A D | spi-mcf-dspi.txt | 16 - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
18 - fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
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| /u-boot/doc/usage/ |
| A D | bootmenu.rst | 22 bootmenu_delay=<delay>
25 <delay>
26 is the autoboot delay in seconds, after which the first
43 The first (optional) argument of the "bootmenu" command is a delay specifier
44 and it overrides the delay value defined by "bootmenu_delay" environment
46 the argument of the "bootmenu" command is not specified, the default delay
47 will be CONFIG_BOOTDELAY. If delay is 0, no menu entries will be shown on
49 be called immediately. If delay is less then 0, bootmenu will be shown and
63 bootmenu 20 # Run bootmenu with autoboot delay 20s
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| /u-boot/drivers/fpga/ |
| A D | lattice.c | 62 void ispVMDelay(unsigned short delay) in ispVMDelay() argument
64 if (delay & 0x8000) in ispVMDelay()
65 delay = (delay & ~0x8000) * 1000; in ispVMDelay()
66 udelay(delay); in ispVMDelay()
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| /u-boot/arch/arm/mach-mvebu/serdes/a38x/ |
| A D | seq_exec.c | 72 u32 delay; in delay_op_execute() local
75 delay = params->wait_time; in delay_op_execute()
77 printf("Delay: %d\n", delay); in delay_op_execute()
79 mdelay(delay); in delay_op_execute()
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