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Searched refs:dev_num (Results 1 – 25 of 59) sorted by relevance

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/u-boot/drivers/ddr/marvell/a38x/
A Dddr3_training_ip_flow.h74 int ddr3_tip_bus_read_modify_write(u32 dev_num,
88 int ddr3_tip_adjust_dqs(u32 dev_num);
89 int ddr3_tip_init_controller(u32 dev_num);
95 int mv_ddr_rl_dqs_burst(u32 dev_num, u32 if_id, u32 freq);
96 int ddr3_tip_legacy_dynamic_read_leveling(u32 dev_num);
98 int ddr3_tip_legacy_dynamic_write_leveling(u32 dev_num);
100 int ddr3_tip_dynamic_write_leveling_supp(u32 dev_num);
101 int ddr3_tip_static_init_controller(u32 dev_num);
102 int ddr3_tip_configure_phy(u32 dev_num);
113 int ddr3_tip_write_cs_result(u32 dev_num, u32 offset);
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A Dddr3_training_ip_prv_if.h31 u8 dev_num, enum mv_ddr_freq freq,
34 u8 dev_num, struct ddr3_device_info *info_ptr);
38 u8 dev_num, u32 if_id, enum mv_ddr_freq freq);
54 u32 dev_num, enum hws_algo_type algo_type);
59 u32 dev_num, struct init_cntr_param *init_cntr_prm);
63 u32 dev_num, int enable);
65 u32 dev_num, struct mv_ddr_topology_map *tm);
67 u32 dev_num, enum mv_ddr_freq frequency,
109 int ddr3_tip_init_config_func(u32 dev_num,
111 int ddr3_tip_register_xsb_info(u32 dev_num,
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A Dddr3_training.c1385 config_func_info[dev_num].tip_set_freq_divider_func(dev_num, if_id, in ddr3_tip_freq_set()
2040 (u8)dev_num, if_id, freq); in ddr3_tip_ddr3_training_main_flow()
2054 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2067 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2099 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2114 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2161 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2182 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2224 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2464 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
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A Dddr3_training_leveling.c219 (dev_num, in ddr3_tip_dynamic_read_leveling()
277 ddr3_tip_bus_write(dev_num, in ddr3_tip_dynamic_read_leveling()
299 (dev_num, if_id)); in ddr3_tip_dynamic_read_leveling()
585 (dev_num, in ddr3_tip_dynamic_per_bit_read_leveling()
602 (dev_num, in ddr3_tip_dynamic_per_bit_read_leveling()
658 (dev_num, in ddr3_tip_dynamic_per_bit_read_leveling()
751 (dev_num, if_id)); in ddr3_tip_dynamic_per_bit_read_leveling()
974 (dev_num, in ddr3_tip_dynamic_write_leveling()
1078 dev_num, in ddr3_tip_dynamic_write_leveling()
1093 (dev_num, in ddr3_tip_dynamic_write_leveling()
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A Dddr3_debug.c111 int ddr3_tip_reg_dump(u32 dev_num) in ddr3_tip_reg_dump() argument
142 (dev_num, if_id, in ddr3_tip_reg_dump()
153 (dev_num, if_id, in ddr3_tip_reg_dump()
195 return config_func_info[dev_num]. in ddr3_tip_get_device_info()
298 int print_device_info(u8 dev_num) in print_device_info() argument
372 ddr3_tip_reg_dump(dev_num); in ddr3_tip_print_log()
844 (dev_num, if_id, in ddr3_tip_print_adll()
1023 (dev_num, in ddr3_tip_run_sweep_test()
1081 print_adll(dev_num, ctrl_adll); in ddr3_tip_run_sweep_test()
1275 print_adll(dev_num, ctrl_adll); in ddr3_tip_run_leveling_sweep_test()
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A Dddr3_training_ip_bist.h35 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
37 int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
44 int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
46 int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
48 int ddr3_tip_run_leveling_sweep_test(int dev_num, u32 repeat_num,
50 int ddr3_tip_print_regs(u32 dev_num);
51 int ddr3_tip_reg_dump(u32 dev_num);
52 int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type,
A Dddr3_training_ip_centralization.h9 int ddr3_tip_centralization_tx(u32 dev_num);
10 int ddr3_tip_centralization_rx(u32 dev_num);
11 int ddr3_tip_print_centralization_result(u32 dev_num);
12 int ddr3_tip_special_rx(u32 dev_num);
A Dddr3_training_ip_engine.c514 (dev_num, access_type, in ddr3_tip_ip_training()
610 (dev_num, access_type, if_id, in ddr3_tip_load_pattern_to_odpg()
616 (dev_num, access_type, if_id, in ddr3_tip_load_pattern_to_odpg()
794 (dev_num, in ddr3_tip_read_training_result()
1182 (dev_num, if_id, in ddr3_tip_ip_training_wrapper()
1278 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_ip_training_wrapper()
1315 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_ip_training_wrapper()
1473 (dev_num, if_id, in ddr3_tip_load_phy_values()
1480 (dev_num, if_id, in ddr3_tip_load_phy_values()
1487 (dev_num, if_id, in ddr3_tip_load_phy_values()
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A Dddr3_training_hw_algo.c77 (dev_num, if_id, in ddr3_tip_write_additional_odt_setting()
201 (dev_num, if_id, in ddr3_tip_vref()
375 (dev_num, if_id, in ddr3_tip_vref()
381 (dev_num, in ddr3_tip_vref()
490 (dev_num, if_id, in ddr3_tip_vref()
496 (dev_num, in ddr3_tip_vref()
533 (dev_num, if_id, in ddr3_tip_vref()
539 (dev_num, in ddr3_tip_vref()
563 (dev_num, if_id, in ddr3_tip_vref()
569 (dev_num, in ddr3_tip_vref()
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A Dddr3_training_centralization.c32 int ddr3_tip_centralization_rx(u32 dev_num) in ddr3_tip_centralization_rx() argument
144 (dev_num, if_id, in ddr3_tip_centralization()
438 ddr3_tip_bus_read(dev_num, if_id, in ddr3_tip_centralization()
460 ddr3_tip_bus_write(dev_num, in ddr3_tip_centralization()
494 int ddr3_tip_special_rx(u32 dev_num) in ddr3_tip_special_rx() argument
555 (dev_num, if_id, in ddr3_tip_special_rx()
624 (dev_num, if_id, in ddr3_tip_special_rx()
632 (dev_num, in ddr3_tip_special_rx()
648 (dev_num, if_id, in ddr3_tip_special_rx()
661 (dev_num, if_id, in ddr3_tip_special_rx()
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A Dddr3_training_pbs.c103 (dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_pbs()
250 (dev_num, in ddr3_tip_pbs()
260 (dev_num, in ddr3_tip_pbs()
280 (dev_num, in ddr3_tip_pbs()
290 (dev_num, in ddr3_tip_pbs()
492 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_pbs()
499 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_pbs()
514 ddr3_tip_ip_training(dev_num, in ddr3_tip_pbs()
530 (dev_num, in ddr3_tip_pbs()
633 (dev_num, in ddr3_tip_pbs()
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A Dddr3_init.h143 int ddr3_tip_enable_init_sequence(u32 dev_num);
152 int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
153 int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
156 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
157 int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
158 int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
160 int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
162 int ddr3_tip_restore_dunit_regs(u32 dev_num);
170 int ddr3_tip_tune_training_params(u32 dev_num,
179 int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
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A Dddr3_training_hw_algo.h9 int ddr3_tip_vref(u32 dev_num);
10 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id);
11 int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap);
A Dddr3_training_ip_pbs.h36 int ddr3_tip_pbs_rx(u32 dev_num);
37 int ddr3_tip_print_all_pbs_result(u32 dev_num);
38 int ddr3_tip_pbs_tx(u32 dev_num);
A Dddr3_training_ip_engine.h33 int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type,
40 int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern);
41 int ddr3_tip_load_all_pattern_to_mem(u32 dev_num);
42 int ddr3_tip_read_training_result(u32 dev_num, u32 if_id,
52 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type,
63 int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type,
A Dmv_ddr_plat.c191 static u32 ddr3_ctrl_get_junc_temp(u8 dev_num) in ddr3_ctrl_get_junc_temp() argument
656 ddr3_tip_init_config_func(dev_num, &config_func); in mv_ddr_sw_db_init()
661 ddr3_tip_dev_attr_init(dev_num); in mv_ddr_sw_db_init()
1368 int ddr3_tip_configure_phy(u32 dev_num) in ddr3_tip_configure_phy() argument
1375 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()
1380 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()
1385 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()
1390 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()
1396 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_configure_phy()
1418 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_configure_phy()
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A Dddr3_training_ip.h136 int ddr3_tip_register_dq_table(u32 dev_num, u32 *table);
137 int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable);
138 int hws_ddr3_tip_init_controller(u32 dev_num,
140 int hws_ddr3_tip_load_topology_map(u32 dev_num,
142 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
A Dddr3_training_leveling.h11 int ddr3_tip_print_wl_supp_result(u32 dev_num);
12 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
A Dddr3_training_ip_db.h90 void ddr3_tip_dev_attr_init(u32 dev_num);
91 u32 ddr3_tip_dev_attr_get(u32 dev_num, enum mv_ddr_dev_attribute attr_id);
92 void ddr3_tip_dev_attr_set(u32 dev_num, enum mv_ddr_dev_attribute attr_id, u32 value);
A Dddr3_init.c17 static int mv_ddr_training_params_set(u8 dev_num);
101 static int mv_ddr_training_params_set(u8 dev_num) in mv_ddr_training_params_set() argument
141 status = ddr3_tip_tune_training_params(dev_num, &params); in mv_ddr_training_params_set()
A Dddr3_training_bist.c12 static int ddr3_tip_bist_operation(u32 dev_num,
20 int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern, in ddr3_tip_bist_activate() argument
74 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id, in ddr3_tip_bist_read_result() argument
86 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
92 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
99 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
105 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
130 ret = ddr3_tip_bist_activate(dev_num, pattern, in hws_ddr3_run_bist()
141 ret = ddr3_tip_bist_activate(dev_num, pattern, in hws_ddr3_run_bist()
167 static int ddr3_tip_bist_operation(u32 dev_num, in ddr3_tip_bist_operation() argument
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/u-boot/include/
A Dnetdev.h34 int bcm_sf2_eth_register(struct bd_info *bis, u8 dev_num);
37 int cs8900_initialize(u8 dev_num, int base_addr);
44 int ep93xx_eth_initialize(u8 dev_num, int base_addr);
46 int ethoc_initialize(u8 dev_num, int base_addr);
54 int ks8851_mll_initialize(u8 dev_num, int base_addr);
55 int lan91c96_initialize(u8 dev_num, int base_addr);
74 int smc91111_initialize(u8 dev_num, int base_addr);
75 int smc911x_initialize(u8 dev_num, int base_addr);
/u-boot/drivers/mmc/
A Dmmc_write.c78 int dev_num = block_dev->devnum; in mmc_berase() local
81 struct mmc *mmc = find_mmc_device(dev_num); in mmc_berase()
88 err = blk_select_hwpart_devnum(IF_TYPE_MMC, dev_num, in mmc_berase()
198 int dev_num = block_dev->devnum; in mmc_bwrite() local
202 struct mmc *mmc = find_mmc_device(dev_num); in mmc_bwrite()
206 err = blk_select_hwpart_devnum(IF_TYPE_MMC, dev_num, block_dev->hwpart); in mmc_bwrite()
/u-boot/drivers/dfu/
A Ddfu_mmc.c32 mmc = find_mmc_device(dfu->data.mmc.dev_num); in mmc_block_op()
34 pr_err("Device MMC %d - not found!", dfu->data.mmc.dev_num); in mmc_block_op()
56 dfu->data.mmc.dev_num, in mmc_block_op()
64 dfu->data.mmc.dev_num, blk_start, blk_count, buf); in mmc_block_op()
81 dfu->data.mmc.dev_num, in mmc_block_op()
88 dfu->data.mmc.dev_num, in mmc_block_op()
351 dfu->data.mmc.dev_num = simple_strtoul(devstr, NULL, 10); in dfu_fill_entity_mmc()
369 mmc = find_mmc_device(dfu->data.mmc.dev_num); in dfu_fill_entity_mmc()
372 dfu->data.mmc.dev_num); in dfu_fill_entity_mmc()
438 dfu->data.mmc.dev_num; in dfu_fill_entity_mmc()
/u-boot/board/samsung/common/
A Dexynos5-dt.c167 int dev_num; in get_dfu_alt_boot() local
172 dev_num = simple_strtoul(devstr, NULL, 10); in get_dfu_alt_boot()
174 mmc = find_mmc_device(dev_num); in get_dfu_alt_boot()

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