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Searched refs:devcfg_base (Results 1 – 3 of 3) sorted by relevance

/u-boot/drivers/fpga/
A Dzynqpl.c166 writel(srclen, &devcfg_base->dma_src_len); in zynq_dma_transfer()
167 writel(dstlen, &devcfg_base->dma_dst_len); in zynq_dma_transfer()
169 isr_status = readl(&devcfg_base->int_sts); in zynq_dma_transfer()
178 readl(&devcfg_base->write_count)); in zynq_dma_transfer()
180 readl(&devcfg_base->read_count)); in zynq_dma_transfer()
212 control = readl(&devcfg_base->ctrl); in zynq_dma_xfer_init()
247 while (!(readl(&devcfg_base->status) & in zynq_dma_xfer_init()
257 isr_status = readl(&devcfg_base->int_sts); in zynq_dma_xfer_init()
273 status = readl(&devcfg_base->status); in zynq_dma_xfer_init()
527 if (!(readl(&devcfg_base->ctrl) & in zynq_decrypt_load()
[all …]
/u-boot/arch/arm/mach-zynq/
A Dcpu.c53 writel(0x757BDF0D, &devcfg_base->unlock); in arch_cpu_init()
54 writel(0xFFFFFFFF, &devcfg_base->rom_shadow); in arch_cpu_init()
77 return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK) in zynq_get_silicon_version()
/u-boot/arch/arm/mach-zynq/include/mach/
A Dhardware.h108 #define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR) macro

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