Searched refs:div0 (Results 1 – 6 of 6) sorted by relevance
| /u-boot/drivers/clk/ |
| A D | clk_zynq.c | 230 u32 clk_ctrl, div0, div1; in zynq_clk_get_dci_rate() local
246 u32 clk_ctrl, div0; in zynq_clk_get_peripheral_rate() local
252 if (!div0) in zynq_clk_get_peripheral_rate()
253 div0 = 1; in zynq_clk_get_peripheral_rate()
292 u32 *div0, u32 *div1) in zynq_clk_calc_peripheral_two_divs() argument
305 *div0 = d0; in zynq_clk_calc_peripheral_two_divs()
321 u32 clk_ctrl, div0 = 0, div1 = 0; in zynq_clk_set_peripheral_rate() local
334 &div0, &div1); in zynq_clk_set_peripheral_rate()
338 if (div0 > ZYNQ_CLK_MAXDIV) in zynq_clk_set_peripheral_rate()
339 div0 = ZYNQ_CLK_MAXDIV; in zynq_clk_set_peripheral_rate()
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| A D | clk_zynqmp.c | 429 u32 clk_ctrl, div0; in zynqmp_clk_get_peripheral_rate() local
441 if (!div0) in zynqmp_clk_get_peripheral_rate()
442 div0 = 1; in zynqmp_clk_get_peripheral_rate()
464 u32 clk_ctrl, div0; in zynqmp_clk_get_wdt_rate() local
476 if (!div0) in zynqmp_clk_get_wdt_rate()
477 div0 = 1; in zynqmp_clk_get_wdt_rate()
505 u32 *div0, u32 *div1) in zynqmp_clk_calc_peripheral_two_divs() argument
518 *div0 = d0; in zynqmp_clk_calc_peripheral_two_divs()
556 &div0, &div1); in zynqmp_clk_set_peripheral_rate()
560 if (div0 > ZYNQ_CLK_MAXDIV) in zynqmp_clk_set_peripheral_rate()
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| /u-boot/arch/arm/mach-s5pc1xx/ |
| A D | clock.c | 141 div = readl(&clk->div0); in s5pc110_get_arm_clk()
161 div = readl(&clk->div0); in s5pc100_get_arm_clk()
182 div = readl(&clk->div0); in get_hclk()
199 div = readl(&clk->div0); in get_pclkd1()
225 div = readl(&clk->div0); in get_hclk_sys()
251 div = readl(&clk->div0); in get_pclk_sys()
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| /u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
| A D | clock.h | 28 unsigned int div0; member
64 unsigned int div0; member
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | clock_sun50i_h6.h | 245 #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) argument
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| /u-boot/arch/arm/lib/ |
| A D | Makefile | 7 lib1funcs.o uldivmod.o div0.o \
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