Searched refs:div4 (Results 1 – 5 of 5) sorted by relevance
32 unsigned int div4; member68 unsigned int div4; member
41 u32 div4; /* 60 */ member
164 "cga-pll1-div4";179 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
354 div4p5_clk: div4.5 {364 clock-names = "pll0_sysclk3", "div4.5";
133 offset = pllctl_reg(data->pll, div4) + (i - 3); in configure_main_pll()
Completed in 37 milliseconds