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Searched refs:div_factor (Results 1 – 4 of 4) sorted by relevance

/u-boot/drivers/video/
A Dssd2828.c255 u32 div_factor = 1, mul_factor, fr = 0; in construct_pll_config() local
259 while (reference_freq_khz / (div_factor + 1) >= 5000) in construct_pll_config()
260 div_factor++; in construct_pll_config()
261 if (div_factor > 31) in construct_pll_config()
262 div_factor = 31; in construct_pll_config()
264 mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor, in construct_pll_config()
276 return (fr << 14) | (div_factor << 8) | mul_factor; in construct_pll_config()
282 u32 div_factor = (pll_config >> 8) & 0x1F; in decode_pll_config() local
285 if (div_factor == 0) in decode_pll_config()
286 div_factor = 1; in decode_pll_config()
[all …]
/u-boot/drivers/clk/
A Dclk-hsdk-cgu.c567 div_factor &= CGU_IDIV_MASK; in idiv_get()
569 pr_debug("current configurarion: %#x (%d)\n", div_factor, div_factor); in idiv_get()
571 if (div_factor == 0) in idiv_get()
574 return parent_rate / div_factor; in idiv_get()
655 u32 div_factor; in idiv_set() local
657 div_factor = parent_rate / rate; in idiv_set()
660 div_factor += 1; in idiv_set()
667 div_factor = CGU_IDIV_MASK; in idiv_set()
670 if (div_factor == 0) { in idiv_set()
674 div_factor = 1; in idiv_set()
[all …]
/u-boot/drivers/i2c/
A Dmeson_i2c.c49 unsigned char div_factor; member
241 div = DIV_ROUND_UP(clk_rate, speed * i2c->data->div_factor); in meson_i2c_set_bus_speed()
287 .div_factor = 4,
291 .div_factor = 4,
295 .div_factor = 3,
/u-boot/arch/arm/mach-omap2/omap5/
A Dhwinit.c201 u32 srcomp_value, mul_factor, div_factor, clk_val, i; in srcomp_enable() local
209 div_factor = srcomp_parameters[sysclk_ind].divide_factor; in srcomp_enable()
216 (div_factor << DIVIDE_FACTOR_XS_SHIFT); in srcomp_enable()
248 (div_factor << DIVIDE_FACTOR_XS_SHIFT); in srcomp_enable()

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