Searched refs:div_val (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/clk/imx/
A D	clk-pll14xx.c	157 u32 tmp, div_val; in clk_pll1416x_set_rate() local 191 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate() 193 writel(div_val, pll->base + 0x4); in clk_pll1416x_set_rate() 223 u32 tmp, div_val; in clk_pll1443x_set_rate() local 234 div_val = readl(pll->base + 8); in clk_pll1443x_set_rate() 236 if (!clk_pll1443x_mpk_change(rate, tmp, div_val)) { in clk_pll1443x_set_rate() 254 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate() 256 writel(div_val, pll->base + 0x4); in clk_pll1443x_set_rate()
/u-boot/arch/arm/mach-imx/imx8m/
A D	clock_imx8mm.c	57 u32 tmp, div_val; in fracpll_configure() local 96 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in fracpll_configure() 98 writel(div_val, pll_base + 4); in fracpll_configure()

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