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/u-boot/drivers/clk/
A Dclk-divider.c81 val = divider->io_divider_val; in clk_divider_recalc_rate()
83 val = readl(divider->reg); in clk_divider_recalc_rate()
85 val >>= divider->shift; in clk_divider_recalc_rate()
86 val &= clk_div_mask(divider->width); in clk_divider_recalc_rate()
89 divider->flags, divider->width); in clk_divider_recalc_rate()
161 divider->width, divider->flags); in clk_divider_set_rate()
166 val = clk_div_mask(divider->width) << (divider->shift + 16); in clk_divider_set_rate()
168 val = readl(divider->reg); in clk_divider_set_rate()
169 val &= ~(clk_div_mask(divider->width) << divider->shift); in clk_divider_set_rate()
171 val |= (u32)value << divider->shift; in clk_divider_set_rate()
[all …]
A Dclk_sandbox_ccf.c152 struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk); in sandbox_clk_composite_divider_recalc_rate() local
157 val = divider->io_divider_val; in sandbox_clk_composite_divider_recalc_rate()
158 val >>= divider->shift; in sandbox_clk_composite_divider_recalc_rate()
159 val &= clk_div_mask(divider->width); in sandbox_clk_composite_divider_recalc_rate()
161 return divider_recalc_rate(clk, parent_rate, val, divider->table, in sandbox_clk_composite_divider_recalc_rate()
162 divider->flags, divider->width); in sandbox_clk_composite_divider_recalc_rate()
A Dclk_stm32h7.c435 u32 divider; in stm32_get_HSI_divider() local
438 divider = readl(&regs->cr) & RCC_CR_HSIDIV_MASK; in stm32_get_HSI_divider()
439 divider = divider >> RCC_CR_HSIDIV_SHIFT; in stm32_get_HSI_divider()
441 return divider; in stm32_get_HSI_divider()
467 u32 divider; in stm32_get_rate() local
486 divider = 0; in stm32_get_rate()
488 divider = stm32_get_HSI_divider(regs); in stm32_get_rate()
490 log_debug("divider %d rate %ld\n", divider, clk_get_rate(&clk)); in stm32_get_rate()
492 return clk_get_rate(&clk) >> divider; in stm32_get_rate()
/u-boot/drivers/clk/imx/
A Dclk-composite-8m.c43 (&composite->clk)->dev->name, parent_rate, divider->reg); in imx8m_clk_composite_divider_recalc_rate()
44 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
45 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
48 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
49 divider->width); in imx8m_clk_composite_divider_recalc_rate()
51 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
55 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
104 val = readl(divider->reg); in imx8m_clk_composite_divider_set_rate()
105 val &= ~((clk_div_mask(divider->width) << divider->shift) | in imx8m_clk_composite_divider_set_rate()
108 val |= (u32)(prediv_value - 1) << divider->shift; in imx8m_clk_composite_divider_set_rate()
[all …]
/u-boot/arch/x86/lib/
A Ddiv64.c57 static u64 _64bit_divide(u64 dividend, u64 divider, u64 *rem_p) in _64bit_divide() argument
65 if (!divider) in _64bit_divide()
66 return 1 / (u32)divider; in _64bit_divide()
70 if (divider > MAX_32BIT_UINT) { in _64bit_divide()
73 *rem_p = divider; in _64bit_divide()
75 result = (u32)dividend / (u32)divider; in _64bit_divide()
77 *rem_p = (u32)dividend % (u32)divider; in _64bit_divide()
82 while (divider <= dividend) { in _64bit_divide()
83 u64 locald = divider; in _64bit_divide()
/u-boot/arch/arm/dts/
A Ddm816x-clocks.dtsi99 compatible = "ti,divider-clock";
117 compatible = "ti,divider-clock";
125 compatible = "ti,divider-clock";
133 compatible = "ti,divider-clock";
141 compatible = "ti,divider-clock";
149 compatible = "ti,divider-clock";
157 compatible = "ti,divider-clock";
165 compatible = "ti,divider-clock";
173 compatible = "ti,divider-clock";
189 compatible = "ti,divider-clock";
A Domap54xx-clocks.dtsi117 compatible = "ti,divider-clock";
134 compatible = "ti,divider-clock";
143 compatible = "ti,divider-clock";
160 compatible = "ti,divider-clock";
190 compatible = "ti,divider-clock";
215 compatible = "ti,divider-clock";
224 compatible = "ti,divider-clock";
233 compatible = "ti,divider-clock";
242 compatible = "ti,divider-clock";
251 compatible = "ti,divider-clock";
[all …]
A Domap44xx-clocks.dtsi148 compatible = "ti,divider-clock";
167 compatible = "ti,divider-clock";
177 compatible = "ti,divider-clock";
209 compatible = "ti,divider-clock";
220 compatible = "ti,divider-clock";
239 compatible = "ti,divider-clock";
250 compatible = "ti,divider-clock";
258 compatible = "ti,divider-clock";
267 compatible = "ti,divider-clock";
276 compatible = "ti,divider-clock";
[all …]
A Ddra7xx-clocks.dtsi214 compatible = "ti,divider-clock";
225 compatible = "ti,divider-clock";
234 compatible = "ti,divider-clock";
245 compatible = "ti,divider-clock";
277 compatible = "ti,divider-clock";
303 compatible = "ti,divider-clock";
347 compatible = "ti,divider-clock";
385 compatible = "ti,divider-clock";
423 compatible = "ti,divider-clock";
436 compatible = "ti,divider-clock";
[all …]
A Dimx8mm-venice-gw700x.dtsi164 gw,voltage-divider-ohms = <22100 1000>;
171 gw,voltage-divider-ohms = <10000 10000>;
178 gw,voltage-divider-ohms = <10000 10000>;
203 gw,voltage-divider-ohms = <10000 10000>;
210 gw,voltage-divider-ohms = <10000 10000>;
229 gw,voltage-divider-ohms = <10000 10000>;
A Dam43xx-clocks.dtsi213 compatible = "ti,divider-clock";
224 compatible = "ti,divider-clock";
235 compatible = "ti,divider-clock";
253 compatible = "ti,divider-clock";
271 compatible = "ti,divider-clock";
289 compatible = "ti,divider-clock";
308 compatible = "ti,divider-clock";
568 compatible = "ti,divider-clock";
591 compatible = "ti,divider-clock";
667 compatible = "ti,divider-clock";
[all …]
A Dimx6qdl-dhcom.dtsi138 lltc,fb-voltage-divider = <100000 110000>;
148 lltc,fb-voltage-divider = <100000 28000>;
157 lltc,fb-voltage-divider = <100000 110000>;
167 lltc,fb-voltage-divider = <100000 93100>;
176 lltc,fb-voltage-divider = <102000 29400>;
184 lltc,fb-voltage-divider = <100000 41200>;
A Domap446x-clocks.dtsi10 compatible = "ti,divider-clock";
A Dam33xx-clocks.dtsi181 compatible = "ti,divider-clock";
190 compatible = "ti,divider-clock";
199 compatible = "ti,divider-clock";
215 compatible = "ti,divider-clock";
231 compatible = "ti,divider-clock";
255 compatible = "ti,divider-clock";
272 compatible = "ti,divider-clock";
510 compatible = "ti,divider-clock";
525 compatible = "ti,divider-clock";
/u-boot/arch/arm/mach-tegra/
A Dclock.c251 u64 divider = parent_rate * 2; in clk_get_divider() local
254 divider += rate - 1; in clk_get_divider()
255 do_div(divider, rate); in clk_get_divider()
257 if ((s64)divider - 2 < 0) in clk_get_divider()
263 return divider - 2; in clk_get_divider()
303 int divider) in get_rate_from_divider() argument
308 do_div(rate, divider + 2); in get_rate_from_divider()
384 divider); in find_best_divider()
391 best_divider = divider; in find_best_divider()
447 int divider; in clock_adjust_periph_pll_div() local
[all …]
/u-boot/arch/powerpc/cpu/mpc8xx/
A Dspeed.c23 uint divider = 1 << (((sccr & SCCR_DFBRG11) >> 11) * 2); in get_clocks() local
41 gd->arch.brg_clk = gd->cpu_clk / divider; in get_clocks()
/u-boot/arch/m68k/cpu/mcf532x/
A Dspeed.c56 int divider; in get_sys_clock() local
60 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); in get_sys_clock()
62 return (FREF / (3 * (1 << divider))); in get_sys_clock()
65 return (FREF / (2 << divider)); in get_sys_clock()
/u-boot/arch/arm/cpu/arm926ejs/mxs/
A Dspl_mem_init.c149 const unsigned char divider = 33; in mxs_mem_init_clock() local
152 const unsigned char divider = 21; in mxs_mem_init_clock() local
162 writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK), in mxs_mem_init_clock()
/u-boot/drivers/serial/
A Dserial_bcm283x_mu.c61 u32 divider; in bcm283x_mu_serial_setbrg() local
66 divider = plat->clock / (baudrate * 8); in bcm283x_mu_serial_setbrg()
69 writel(divider - 1, &regs->baud); in bcm283x_mu_serial_setbrg()
A Dserial_pxa.c63 uint32_t divider = pxa_uart_get_baud_divider(baudrate); in pxa_setbrg_common() local
64 if (!divider) in pxa_setbrg_common()
76 writel(divider & 0xff, &uart_regs->dll); in pxa_setbrg_common()
77 writel(divider >> 8, &uart_regs->dlh); in pxa_setbrg_common()
/u-boot/drivers/mmc/
A Dmxcmmc.c424 unsigned int divider; in mxcmci_set_clk_rate() local
429 for (divider = 1; divider <= 0xF; divider++) { in mxcmci_set_clk_rate()
432 x = (clk_in / (divider + 1)); in mxcmci_set_clk_rate()
440 if (divider < 0x10) in mxcmci_set_clk_rate()
449 writel((prescaler << 4) | divider, &host->base->clk_rate); in mxcmci_set_clk_rate()
/u-boot/drivers/i2c/
A Dfsl_i2c.c89 unsigned short divider; member
126 ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX); in set_i2c_bus_speed() local
148 speed = i2c_clk / divider; /* Fake something */ in set_i2c_bus_speed()
159 if (c_div > divider && c_div < est_div) { in set_i2c_bus_speed()
184 debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr); in set_i2c_bus_speed()
193 if (fsl_i2c_speed_map[i].divider >= divider) { in set_i2c_bus_speed()
197 speed = i2c_clk / fsl_i2c_speed_map[i].divider; in set_i2c_bus_speed()
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A DKconfig501 int "Platform clock divider"
508 This is the divider that is used to derive Platform clock from
513 int "DSPI clock divider"
521 int "DUART clock divider"
531 int "I2C clock divider"
540 This is the divider that is used to derive I2C clock from Platform
544 int "IFC clock divider"
553 This is the divider that is used to derive IFC clock from Platform
557 int "LPUART clock divider"
565 int "SDHC clock divider"
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/u-boot/drivers/clk/ti/
A DKconfig20 bool "TI divider clock driver"
23 This enables the divider clock driver support on TI's SoCs.
A DMakefile10 obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o

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