Searched refs:divm (Results 1 – 8 of 8) sorted by relevance
| /u-boot/arch/arm/mach-tegra/ |
| A D | clock.c | 92 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, in clock_ll_read_pll() argument
105 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask; in clock_ll_read_pll()
116 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, in clock_start_pll() argument
150 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift); in clock_start_pll()
539 u32 base, divm; in clock_get_rate() local
556 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask; in clock_get_rate()
570 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask; in clock_get_rate()
571 do_div(rate, divm); in clock_get_rate()
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| A D | cpu.c | 172 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, in pllx_set_rate() argument
189 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift); in pllx_set_rate()
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| /u-boot/arch/arm/include/asm/arch-tegra/ |
| A D | clock.h | 63 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
90 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
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| A D | warmboot.h | 71 u32 divm:5; member
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| /u-boot/arch/arm/mach-tegra/tegra20/ |
| A D | warmboot.c | 154 u32 divm, divn, divp, cpcon, lfcon; in warmboot_save_sdram_params() local
156 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp, in warmboot_save_sdram_params()
159 scratch2.pllm_base_divm = divm; in warmboot_save_sdram_params()
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| /u-boot/drivers/clk/ |
| A D | clk_stm32mp1.c | 903 int divm, divn; in pll_get_fvco() local
925 ((unsigned long long)(divm + 1)) << 13); in pll_get_fvco()
927 fvco = (ulong)(refclk * (divn + 1) / (divm + 1)); in pll_get_fvco()
1324 u32 divm, divn, divp, frac; in stm32mp1_pll1_opp() local
1356 for (divm = DIVM_MAX; divm >= DIVM_MIN; divm--) { in stm32mp1_pll1_opp()
1357 post_divm = (u32)(input_freq / (divm + 1)); in stm32mp1_pll1_opp()
1362 freq = output_freq * (divm + 1) * (divp + 1); in stm32mp1_pll1_opp()
1388 pllcfg[PLLCFG_M] = divm; in stm32mp1_pll1_opp()
1698 int divm, divn, divy; in pll_set_rate() local
1719 divm = pllcfg[PLLCFG_M]; in pll_set_rate()
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| A D | clk_stm32h7.c | 325 u8 divm; member
338 .divm = 4,
399 pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT; in configure_clocks()
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| /u-boot/arch/arm/mach-tegra/tegra124/ |
| A D | clock.c | 1069 u32 divm, divn, divp, cpcon; in clock_set_display_rate() local
1089 for (divm = 1; divm < max_m && best_diff; divm++) { in clock_set_display_rate()
1090 cf = ref / divm; in clock_set_display_rate()
1110 best_m = divm; in clock_set_display_rate()
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