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/u-boot/drivers/clk/
A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
531 divm1 = readl(&regs->pllckselr) & RCC_PLLCKSELR_DIVM1_MASK; in stm32_get_PLL1_rate()
532 divm1 = divm1 >> RCC_PLLCKSELR_DIVM1_SHIFT; in stm32_get_PLL1_rate()
548 vco = (pllsrc / divm1) * divn1; in stm32_get_PLL1_rate()
549 rate = (pllsrc * fracn1) / (divm1 * 8192); in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()

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