Searched refs:divn (Results 1 – 11 of 11) sorted by relevance
| /u-boot/arch/arm/mach-uniphier/clk/ |
| A D | pll-base-ld20.c | 33 unsigned int ssc_rate, unsigned int divn) in uniphier_ld20_sscpll_init() argument
43 divn * 512)); in uniphier_ld20_sscpll_init()
50 divn * 512)); in uniphier_ld20_sscpll_init()
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| A D | pll.h | 15 unsigned int ssc_rate, unsigned int divn);
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| /u-boot/arch/arm/include/asm/arch-tegra/ |
| A D | clock.h | 63 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
90 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
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| A D | warmboot.h | 73 u32 divn:10; member
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| /u-boot/arch/arm/mach-tegra/ |
| A D | cpu.c | 172 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, in pllx_set_rate() argument
190 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); in pllx_set_rate()
204 if (divn > 600) in pllx_set_rate()
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| A D | clock.c | 92 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, in clock_ll_read_pll() argument
106 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask; in clock_ll_read_pll()
116 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, in clock_start_pll() argument
150 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift); in clock_start_pll()
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| /u-boot/arch/arm/mach-tegra/tegra20/ |
| A D | warmboot.c | 154 u32 divm, divn, divp, cpcon, lfcon; in warmboot_save_sdram_params() local
156 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp, in warmboot_save_sdram_params()
160 scratch2.pllm_base_divn = divn; in warmboot_save_sdram_params()
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| A D | warmboot_avp.c | 168 pllx_base.divn = scratch3.pllx_base_divn; in wb_start()
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| /u-boot/drivers/clk/ |
| A D | clk_stm32mp1.c | 903 int divm, divn; in pll_get_fvco() local
1324 u32 divm, divn, divp, frac; in stm32mp1_pll1_opp() local
1364 if (divn < DIVN_MIN || divn > DIVN_MAX) in stm32mp1_pll1_opp()
1368 ((divn + 1) * FRAC_MAX)); in stm32mp1_pll1_opp()
1374 vco = (post_divm * (divn + 1)) + in stm32mp1_pll1_opp()
1389 pllcfg[PLLCFG_N] = divn; in stm32mp1_pll1_opp()
1698 int divm, divn, divy; in pll_set_rate() local
1734 divn = (value >> 13) - 1; in pll_set_rate()
1735 if (divn < DIVN_MIN || in pll_set_rate()
1740 fracv = value - ((divn + 1) << 13); in pll_set_rate()
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| A D | clk_stm32h7.c | 326 u16 divn; member
339 .divn = 80,
405 pll1divr |= (sys_pll_psc.divn - 1); in configure_clocks()
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| /u-boot/arch/arm/mach-tegra/tegra124/ |
| A D | clock.c | 1069 u32 divm, divn, divp, cpcon; in clock_set_display_rate() local
1096 divn = vco / cf; in clock_set_display_rate()
1097 if (divn >= max_n) in clock_set_display_rate()
1100 diff = vco - divn * cf; in clock_set_display_rate()
1101 if (divn + 1 < max_n && diff > cf / 2) { in clock_set_display_rate()
1102 divn++; in clock_set_display_rate()
1111 best_n = divn; in clock_set_display_rate()
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