Searched refs:divp (Results 1 – 9 of 9) sorted by relevance
| /u-boot/arch/arm/include/asm/arch-tegra/ |
| A D | clock.h | 64 u32 divp, u32 cpcon, u32 lfcon);
91 u32 *divp, u32 *cpcon, u32 *lfcon);
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| A D | warmboot.h | 75 u32 divp:3; member
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| /u-boot/arch/arm/mach-tegra/tegra20/ |
| A D | warmboot.c | 154 u32 divm, divn, divp, cpcon, lfcon; in warmboot_save_sdram_params() local
156 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp, in warmboot_save_sdram_params()
161 scratch2.pllm_base_divp = divp; in warmboot_save_sdram_params()
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| A D | warmboot_avp.c | 172 pllx_base.divp = scratch3.pllx_base_divp; in wb_start()
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| /u-boot/arch/arm/mach-tegra/ |
| A D | cpu.c | 173 u32 divp, u32 cpcon) in pllx_set_rate() argument
190 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); in pllx_set_rate()
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| A D | clock.c | 93 u32 *divp, u32 *cpcon, u32 *lfcon) in clock_ll_read_pll() argument
107 *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask; in clock_ll_read_pll()
117 u32 divp, u32 cpcon, u32 lfcon) in clock_start_pll() argument
151 data |= divp << pllinfo->p_shift; in clock_start_pll()
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| /u-boot/drivers/clk/ |
| A D | clk_stm32h7.c | 327 u8 divp; member
340 .divp = 2,
404 pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT; in configure_clocks()
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| A D | clk_stm32mp1.c | 1324 u32 divm, divn, divp, frac; in stm32mp1_pll1_opp() local
1361 for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) { in stm32mp1_pll1_opp()
1362 freq = output_freq * (divm + 1) * (divp + 1); in stm32mp1_pll1_opp()
1382 freq = vco / (divp + 1); in stm32mp1_pll1_opp()
1390 pllcfg[PLLCFG_P] = divp; in stm32mp1_pll1_opp()
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| /u-boot/arch/arm/mach-tegra/tegra124/ |
| A D | clock.c | 1069 u32 divm, divn, divp, cpcon; in clock_set_display_rate() local
1077 for (divp = 0, vco = frequency; vco < min_vco && divp < max_p; divp++) in clock_set_display_rate()
1086 best_p = divp; in clock_set_display_rate()
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