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/u-boot/drivers/clk/
A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
536 divp1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVP1_MASK; in stm32_get_PLL1_rate()
537 divp1 = (divp1 >> RCC_PLL1DIVR_DIVP1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
558 return (vco + rate) / divp1; in stm32_get_PLL1_rate()

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