Searched refs:divq (Results 1 – 5 of 5) sorted by relevance
| /u-boot/drivers/clk/analogbits/ |
| A D | wrpll-cln28hpc.c | 147 u8 divq = 0; in __wrpll_calc_divq() local
156 divq = 1; in __wrpll_calc_divq()
159 divq = ilog2(MAX_DIVQ_DIVISOR); in __wrpll_calc_divq()
162 divq = ilog2(s); in __wrpll_calc_divq()
163 *vco_rate = (u64)target_rate << divq; in __wrpll_calc_divq()
167 return divq; in __wrpll_calc_divq()
227 u8 fbdiv, divq, best_r, r; in wrpll_configure_for_rate() local
255 divq = __wrpll_calc_divq(target_rate, &target_vco_rate); in wrpll_configure_for_rate()
256 if (!divq) in wrpll_configure_for_rate()
258 c->divq = divq; in wrpll_configure_for_rate()
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| /u-boot/include/linux/clk/ |
| A D | analogbits-wrpll-cln28hpc.h | 60 u8 divq; member
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| /u-boot/arch/arm/mach-imx/imx8m/ |
| A D | clock_imx8mq.c | 86 u32 divr1, divr2, divf1, divf2, divq, div; in decode_sscg_pll() local
236 divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >> in decode_sscg_pll()
246 (divr2 + 1) * (divf2 + 1) / (divq + 1); in decode_sscg_pll()
659 u32 val_cfg0, val_cfg1, divq; in frac_pll_init() local
669 divq = 0; in frac_pll_init()
672 divq = 1; in frac_pll_init()
677 FRAC_PLL_OUTPUT_DIV_VAL(divq); in frac_pll_init()
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| /u-boot/drivers/clk/ |
| A D | clk_stm32h7.c | 328 u8 divq; member
341 .divq = 2,
403 pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT; in configure_clocks()
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| /u-boot/drivers/clk/sifive/ |
| A D | fu540-prci.c | 294 c->divq = v; in __prci_wrpll_unpack()
328 r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT; in __prci_wrpll_pack()
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