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Searched refs:divr (Results 1 – 4 of 4) sorted by relevance

/u-boot/include/linux/clk/
A Danalogbits-wrpll-cln28hpc.h59 u8 divr; member
/u-boot/drivers/clk/analogbits/
A Dwrpll-cln28hpc.c298 c->divr = best_r - 1; in wrpll_configure_for_rate()
343 n = div_u64(n, c->divr + 1); in wrpll_calc_output_rate()
/u-boot/drivers/clk/
A Dclk_stm32h7.c329 u8 divr; member
342 .divr = 2,
402 pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT; in configure_clocks()
/u-boot/drivers/clk/sifive/
A Dfu540-prci.c286 c->divr = v; in __prci_wrpll_unpack()
326 r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT; in __prci_wrpll_pack()

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