Searched refs:divr1 (Results 1 – 2 of 2) sorted by relevance
| /u-boot/drivers/clk/ |
| A D | clk_stm32h7.c | 505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
|
| /u-boot/arch/arm/mach-imx/imx8m/ |
| A D | clock_imx8mq.c | 86 u32 divr1, divr2, divf1, divf2, divq, div; in decode_sscg_pll() local
228 divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >> in decode_sscg_pll()
245 pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) / in decode_sscg_pll()
|
Completed in 5 milliseconds