Searched refs:dqs_dly (Results 1 – 5 of 5) sorted by relevance
| /u-boot/arch/mips/mach-mtmips/ |
| A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
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| A D | ddr_init.c | 70 u32 dq_dly, u32 dqs_dly, mc_reset_t mc_reset, u32 bw) in mc_ddr_init() argument
84 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in mc_ddr_init()
109 param->dqs_dly, param->mc_reset, IND_SDRAM_WIDTH_16BIT); in ddr1_init()
120 param->dqs_dly, param->mc_reset, bw); in ddr1_init()
140 param->dqs_dly, param->mc_reset, bw); in ddr1_init()
154 param->dqs_dly, param->mc_reset, IND_SDRAM_WIDTH_16BIT); in ddr2_init()
165 param->dqs_dly, param->mc_reset, bw); in ddr2_init()
197 param->dqs_dly, param->mc_reset, bw); in ddr2_init()
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| /u-boot/arch/mips/mach-mtmips/include/mach/ |
| A D | ddr.h | 42 u32 dqs_dly; member
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| /u-boot/arch/mips/mach-mtmips/mt7620/ |
| A D | dram.c | 88 param.dqs_dly = DDR2_DQS_DLY; in mt7620_dram_init()
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| /u-boot/arch/mips/mach-mtmips/mt7628/ |
| A D | ddr.c | 150 param.dqs_dly = DDR2_DQS_DLY; in mt7628_ddr_init()
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