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Searched refs:dram (Results 1 – 25 of 93) sorted by relevance

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/u-boot/arch/arm/mach-lpc32xx/
A Ddram.c25 void ddr_init(struct emc_dram_settings *dram) in ddr_init() argument
37 writel(dram->cmddelay, &clk->sdramclk_ctrl); in ddr_init()
38 writel(dram->config0, &emc->config0); in ddr_init()
39 writel(dram->rascas0, &emc->rascas0); in ddr_init()
40 writel(dram->rdconfig, &emc->read_config); in ddr_init()
42 writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); in ddr_init()
49 writel(dram->trrd, &emc->t_rrd); in ddr_init()
50 writel(dram->tmrd, &emc->t_mrd); in ddr_init()
51 writel(dram->tcdlr, &emc->t_cdlr); in ddr_init()
68 readl(EMC_DYCS0_BASE | dram->mode); in ddr_init()
[all …]
A DMakefile8 obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun4i.c62 struct sunxi_dram_reg *dram = in mctl_ddr3_reset() local
372 u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1); in mctl_set_dqs_gating_delay()
374 u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1); in mctl_set_dqs_gating_delay()
382 writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1); in mctl_set_dqs_gating_delay()
383 writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1); in mctl_set_dqs_gating_delay()
399 reg_val = readl(&dram->csr); in dramc_scan_readpipe()
546 writel(reg_val, &dram->zqcr0); in mctl_set_impedance()
551 writel(reg_val, &dram->zqcr0); in mctl_set_impedance()
620 writel(reg_val, &dram->dcr); in dramc_init_helper()
650 writel(reg_val, &dram->mr); in dramc_init_helper()
[all …]
/u-boot/drivers/ram/rockchip/
A Dsdram_px30.c149 &dram->cru->softrst_con[1]); in rkclk_ddr_reset()
151 &dram->cru->softrst_con[2]); in rkclk_ddr_reset()
186 &dram->cru->pll[1].con1); in rkclk_set_dpll()
377 phy_dram_set_bw(dram->phy, bw); in dram_set_bw()
491 rkclk_ddr_reset(dram, 1, 1, 1, 1); in sdram_init_()
498 rkclk_ddr_reset(dram, 1, 1, 1, 0); in sdram_init_()
502 rkclk_ddr_reset(dram, 1, 1, 0, 0); in sdram_init_()
504 phy_soft_reset(dram->phy); in sdram_init_()
531 if (check_rd_gate(dram)) { in sdram_init_()
550 if (check_rd_gate(dram)) { in sdram_init_()
[all …]
A Dsdram_rk3328.c72 &dram->cru->softrst_con[5]); in rkclk_ddr_reset()
107 &dram->cru->dpll_con[1]); in rkclk_set_dpll()
122 void __iomem *phy_base = dram->phy; in rkclk_configure_ddr()
348 rkclk_ddr_reset(dram, 1, 1, 1, 1); in sdram_init()
355 rkclk_ddr_reset(dram, 1, 1, 1, 0); in sdram_init()
359 rkclk_ddr_reset(dram, 1, 1, 0, 0); in sdram_init()
361 phy_soft_reset(dram->phy); in sdram_init()
363 rkclk_ddr_reset(dram, 1, 0, 0, 0); in sdram_init()
372 rkclk_ddr_reset(dram, 0, 0, 0, 0); in sdram_init()
388 rx_deskew_switch_adjust(dram); in sdram_init()
[all …]
A Dsdram_rk322x.c368 struct rk322x_grf *grf = dram->grf; in phy_softreset()
384 struct rk322x_grf *grf = dram->grf; in set_bw()
616 set_bw(dram, 2); in dram_cap_detect()
621 set_bw(dram, 1); in dram_cap_detect()
623 phy_softreset(dram); in dram_cap_detect()
625 if (data_training(&dram->chan[0])) { in dram_cap_detect()
692 ret = clk_set_rate(&dram->ddr_clk, in sdram_init()
699 phy_pctrl_reset(dram->cru, dram->chan[0].phy); in sdram_init()
701 pctl_cfg(dram->chan[0].pctl, sdram_params, dram->grf); in sdram_init()
702 phy_cfg(&dram->chan[0], sdram_params); in sdram_init()
[all …]
A Dsdram_rk3399.c231 return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0; in get_ddrc0_con()
839 dram->pwrup_srefresh_exit[0]); in pctl_start()
877 dram->pwrup_srefresh_exit[1]); in pctl_start()
1657 &dram->cic->cic_ctrl0); in switch_to_phy_index1()
1858 set_ddr_stride(dram->pmusgrf, 0x17); in lpddr4_mr_detect()
1860 set_ddr_stride(dram->pmusgrf, 0x18); in lpddr4_mr_detect()
2925 &dram->chan[channel]; in sdram_init()
2935 pctl_start(dram, params, 3); in sdram_init()
2946 ret = dram->ops->data_training_first(dram, ch, in sdram_init()
3006 dram_all_config(dram, params); in sdram_init()
[all …]
A Dsdram_rk3188.c561 ddr_rank_2_row15en(dram->grf, 0); in dram_all_config()
563 ddr_rank_2_row15en(dram->grf, 1); in dram_all_config()
565 writel(sys_reg, &dram->pmu->sys_reg[2]); in dram_all_config()
576 ddr_rank_2_row15en(dram->grf, 0); in sdram_rank_bw_detect()
599 dram->grf); in sdram_rank_bw_detect()
609 ddr_phy_ctl_reset(dram->cru, channel, 1); in sdram_rank_bw_detect()
611 ddr_phy_ctl_reset(dram->cru, channel, 0); in sdram_rank_bw_detect()
657 ddr_rank_2_row15en(dram->grf, 1); in sdram_col_row_detect()
713 static int sdram_init(struct dram_info *dram, in sdram_init() argument
737 phy_pctrl_reset(dram->cru, publ, channel); in sdram_init()
[all …]
A Dsdram_rk3288.c618 writel(sys_reg, &dram->pmu->sys_reg[2]); in dram_all_config()
653 dram->grf); in sdram_rank_bw_detect()
663 ddr_phy_ctl_reset(dram->cru, channel, 1); in sdram_rank_bw_detect()
665 ddr_phy_ctl_reset(dram->cru, channel, 0); in sdram_rank_bw_detect()
785 static int sdram_init(struct dram_info *dram, in sdram_init() argument
816 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x17); in sdram_init()
818 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x1a); in sdram_init()
819 phy_pctrl_reset(dram->cru, publ, channel); in sdram_init()
824 pctl_cfg(channel, pctl, sdram_params, dram->grf); in sdram_init()
858 sdram_params->ch[channel].bw, dram->grf); in sdram_init()
[all …]
/u-boot/arch/arm/mach-uniphier/clk/
A DMakefile5 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
6 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
7 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
8 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
9 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
10 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
/u-boot/arch/arm/mach-mvebu/
A Dcpu.c546 const struct mbus_dram_target_info *dram; in ahci_mvebu_mbus_config() local
553 dram = mvebu_mbus_dram_info(); in ahci_mvebu_mbus_config()
561 for (i = 0; i < dram->num_cs; i++) { in ahci_mvebu_mbus_config()
562 const struct mbus_dram_window *cs = dram->cs + i; in ahci_mvebu_mbus_config()
565 (dram->mbus_dram_target_id << 4) | 1, in ahci_mvebu_mbus_config()
607 const struct mbus_dram_target_info *dram) in xhci_mvebu_mbus_config() argument
616 for (i = 0; i < dram->num_cs; i++) { in xhci_mvebu_mbus_config()
617 const struct mbus_dram_window *cs = dram->cs + i; in xhci_mvebu_mbus_config()
621 (dram->mbus_dram_target_id << 4) | 1, in xhci_mvebu_mbus_config()
631 const struct mbus_dram_target_info *dram; in board_xhci_enable() local
[all …]
/u-boot/arch/x86/dts/
A Dgalileo.dts51 dram-width = <DRAM_WIDTH_X8>;
52 dram-speed = <DRAM_FREQ_800>;
53 dram-type = <DRAM_TYPE_DDR3>;
63 dram-density = <DRAM_DENSITY_1G>;
64 dram-cl = <6>;
65 dram-ras = <0x0000927c>;
66 dram-wtr = <0x00002710>;
67 dram-rrd = <0x00002710>;
68 dram-faw = <0x00009c40>;
/u-boot/drivers/ata/
A Dmvsata_ide.c108 const struct mbus_dram_target_info *dram; in mvsata_ide_conf_mbus_windows() local
111 dram = mvebu_mbus_dram_info(); in mvsata_ide_conf_mbus_windows()
119 for (i = 0; i < dram->num_cs; i++) { in mvsata_ide_conf_mbus_windows()
120 const struct mbus_dram_window *cs = dram->cs + i; in mvsata_ide_conf_mbus_windows()
122 (dram->mbus_dram_target_id << 4) | 1, in mvsata_ide_conf_mbus_windows()
/u-boot/drivers/mmc/
A Dmv_sdhci.c20 const struct mbus_dram_target_info *dram; in sdhci_mvebu_mbus_config() local
23 dram = mvebu_mbus_dram_info(); in sdhci_mvebu_mbus_config()
30 for (i = 0; i < dram->num_cs; i++) { in sdhci_mvebu_mbus_config()
31 const struct mbus_dram_window *cs = dram->cs + i; in sdhci_mvebu_mbus_config()
35 (dram->mbus_dram_target_id << 4) | 1, in sdhci_mvebu_mbus_config()
/u-boot/drivers/usb/host/
A Dehci-marvell.c58 const struct mbus_dram_target_info *dram; in usb_brg_adrdec_setup() local
61 dram = mvebu_mbus_dram_info(); in usb_brg_adrdec_setup()
68 for (i = 0; i < dram->num_cs; i++) { in usb_brg_adrdec_setup()
69 const struct mbus_dram_window *cs = dram->cs + i; in usb_brg_adrdec_setup()
73 (dram->mbus_dram_target_id << 4) | 1, in usb_brg_adrdec_setup()
/u-boot/drivers/ddr/imx/imx8m/
A DKconfig5 bool "imx8m dram"
26 hex "Define the base address for saved dram timing"
28 after DRAM is trained, need to save the dram related timming
/u-boot/drivers/video/
A Dmvebu_lcd.c104 const struct mbus_dram_target_info *dram; in mvebu_lcd_conf_mbus_registers() local
107 dram = mvebu_mbus_dram_info(); in mvebu_lcd_conf_mbus_registers()
117 for (i = 0; i < dram->num_cs; i++) { in mvebu_lcd_conf_mbus_registers()
118 const struct mbus_dram_window *cs = dram->cs + i; in mvebu_lcd_conf_mbus_registers()
120 (dram->mbus_dram_target_id << 4) | 1, in mvebu_lcd_conf_mbus_registers()
/u-boot/arch/mips/mach-bmips/
A DMakefile3 obj-y += dram.o
/u-boot/arch/riscv/cpu/generic/
A DMakefile5 obj-y += dram.o
/u-boot/arch/arm/mach-mvebu/armada8k/
A DMakefile5 obj-y = cpu.o cache_llc.o dram.o
/u-boot/arch/arm/cpu/arm926ejs/armada100/
A DMakefile7 obj-y = cpu.o timer.o dram.o
/u-boot/arch/mips/mach-mtmips/mt7620/
A Dinit.c150 u32 val, ver, eco, pkg, dram, chipmode; in print_cpuinfo() local
159 dram = (val & DRAM_TYPE_M) >> DRAM_TYPE_S; in print_cpuinfo()
169 printf("Boot: %s, %s\n", dram_type[dram], bootdev); in print_cpuinfo()
A DMakefile5 obj-y += dram.o
/u-boot/arch/arm/include/asm/arch-lpc32xx/
A Dsys_proto.h20 void ddr_init(const struct emc_dram_settings *dram);
/u-boot/arch/riscv/cpu/fu540/
A DMakefile9 obj-y += dram.o

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