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Searched refs:dram_clk_cfg (Results 1 – 12 of 12) sorted by relevance

/u-boot/arch/arm/mach-sunxi/
A Ddram_sunxi_dw.c433 clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); in mctl_sys_init()
438 clrsetbits_le32(&ccm->dram_clk_cfg, in mctl_sys_init()
446 clrsetbits_le32(&ccm->dram_clk_cfg, in mctl_sys_init()
453 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
460 setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); in mctl_sys_init()
A Ddram_sun8i_a83t.c403 clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31); in mctl_sys_init()
407 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK, in mctl_sys_init()
410 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
A Ddram_sun8i_a33.c311 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK, in mctl_sys_init()
314 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
A Ddram_sun50i_h6.c168 clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); in mctl_sys_init()
178 writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg); in mctl_sys_init()
179 setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE); in mctl_sys_init()
192 setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); in mctl_sys_init()
A Ddram_sun9i.c294 writel((3 << 12) | (1 << 16), &ccm->dram_clk_cfg); in mctl_sys_init()
298 } while (readl(&ccm->dram_clk_cfg) & (1 << 16)); in mctl_sys_init()
299 setbits_le32(&ccm->dram_clk_cfg, (1 << 31)); in mctl_sys_init()
A Ddram_sun6i.c39 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK, in mctl_sys_init()
42 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
A Ddram_sun50i_h616.c110 clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); in mctl_sys_init()
120 writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg); in mctl_sys_init()
136 setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); in mctl_sys_init()
A Ddram_sun8i_a23.c226 setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); in mctl_init()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Dclock_sun9i.h65 u32 dram_clk_cfg; /* 0x484 DRAM (controller) clock config */ member
A Dclock_sun8i_a83t.h64 u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ member
A Dclock_sun50i_h6.h137 u32 dram_clk_cfg; /* 0x800 DRAM clock control */ member
A Dclock_sun6i.h70 u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ member

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