| /u-boot/drivers/ddr/imx/imx8m/ |
| A D | ddrphy_train.c | 13 int ddr_cfg_phy(struct dram_timing_info *dram_timing) in ddr_cfg_phy() argument
23 dram_cfg = dram_timing->ddrphy_cfg; in ddr_cfg_phy()
24 num = dram_timing->ddrphy_cfg_num; in ddr_cfg_phy()
32 fsp_msg = dram_timing->fsp_msg; in ddr_cfg_phy()
33 for (i = 0; i < dram_timing->fsp_msg_num; i++) { in ddr_cfg_phy()
88 dram_cfg = dram_timing->ddrphy_pie; in ddr_cfg_phy()
89 num = dram_timing->ddrphy_pie_num; in ddr_cfg_phy()
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| A D | ddr_init.c | 94 int ddr_init(struct dram_timing_info *dram_timing) in ddr_init() argument
120 initial_drate = dram_timing->fsp_msg[0].drate; in ddr_init()
129 ddr_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); in ddr_init()
174 ret = ddr_cfg_phy(dram_timing); in ddr_init()
194 update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1); in ddr_init()
249 dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); in ddr_init()
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| /u-boot/board/gateworks/venice/ |
| A D | spl.c | 40 struct dram_timing_info *dram_timing; in spl_dram_init() local
44 dram_timing = &dram_timing_1gb; in spl_dram_init()
47 dram_timing = &dram_timing_4gb; in spl_dram_init()
51 dram_timing = &dram_timing_1gb; in spl_dram_init()
56 ddr_init(dram_timing); in spl_dram_init()
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| /u-boot/board/technexion/pico-imx8mq/ |
| A D | spl.c | 52 struct dram_timing_info *dram_timing; in spl_dram_init() local
71 dram_timing = &dram_timing_4gb; in spl_dram_init()
75 dram_timing = &dram_timing_3gb; in spl_dram_init()
79 dram_timing = &dram_timing_2gb; in spl_dram_init()
83 dram_timing = &dram_timing_1gb; in spl_dram_init()
91 ddr_init(dram_timing); in spl_dram_init()
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| /u-boot/board/google/imx8mq_phanbell/ |
| A D | lpddr4_timing_1g.c | 1719 struct dram_timing_info dram_timing = { variable
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| A D | spl.c | 33 ddr_init(&dram_timing); in spl_dram_init()
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| /u-boot/board/beacon/imx8mn/ |
| A D | lpddr4_2g_timing.c | 1428 struct dram_timing_info dram_timing = { variable
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| A D | lpddr4_timing.c | 1421 struct dram_timing_info dram_timing = { variable
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| A D | spl.c | 44 ddr_init(&dram_timing); in spl_dram_init()
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| /u-boot/board/phytec/phycore_imx8mm/ |
| A D | lpddr4_timing.c | 1834 struct dram_timing_info dram_timing = { variable
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| A D | spl.c | 44 ddr_init(&dram_timing); in spl_dram_init()
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| /u-boot/board/phytec/phycore_imx8mp/ |
| A D | lpddr4_timing.c | 1837 struct dram_timing_info dram_timing = { variable
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| A D | spl.c | 33 ddr_init(&dram_timing); in spl_dram_init()
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| /u-boot/board/freescale/imx8mn_evk/ |
| A D | ddr4_timing.c | 1201 struct dram_timing_info dram_timing = { variable
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| A D | spl.c | 38 ddr_init(&dram_timing); in spl_dram_init()
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| /u-boot/board/freescale/imx8mp_evk/ |
| A D | lpddr4_timing.c | 1836 struct dram_timing_info dram_timing = { variable
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| A D | spl.c | 42 ddr_init(&dram_timing); in spl_dram_init()
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| /u-boot/board/toradex/verdin-imx8mm/ |
| A D | lpddr4_timing.c | 1838 struct dram_timing_info dram_timing = { variable
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| A D | spl.c | 55 ddr_init(&dram_timing); in spl_dram_init()
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| /u-boot/board/beacon/imx8mm/ |
| A D | spl.c | 44 ddr_init(&dram_timing); in spl_dram_init()
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| A D | lpddr4_timing.c | 1969 struct dram_timing_info dram_timing = { variable
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| /u-boot/board/freescale/imx8mm_evk/ |
| A D | spl.c | 49 ddr_init(&dram_timing); in spl_dram_init()
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| A D | lpddr4_timing.c | 1969 struct dram_timing_info dram_timing = { variable
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| /u-boot/board/freescale/imx8mq_evk/ |
| A D | spl.c | 40 ddr_init(&dram_timing); in spl_dram_init()
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| A D | lpddr4_timing.c | 1314 struct dram_timing_info dram_timing = { variable
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