Home
last modified time | relevance | path

Searched refs:dramtmg (Results 1 – 11 of 11) sorted by relevance

/u-boot/arch/arm/mach-sunxi/dram_timings/
A Dh616_ddr3_1333.c58 &mctl_ctl->dramtmg[0]); in mctl_set_timing_params()
61 &mctl_ctl->dramtmg[2]); in mctl_set_timing_params()
64 &mctl_ctl->dramtmg[4]); in mctl_set_timing_params()
66 &mctl_ctl->dramtmg[5]); in mctl_set_timing_params()
70 &mctl_ctl->dramtmg[8]); in mctl_set_timing_params()
71 writel(0x00020208, &mctl_ctl->dramtmg[9]); in mctl_set_timing_params()
72 writel(0xE0C05, &mctl_ctl->dramtmg[10]); in mctl_set_timing_params()
73 writel(0x440C021C, &mctl_ctl->dramtmg[11]); in mctl_set_timing_params()
74 writel(8, &mctl_ctl->dramtmg[12]); in mctl_set_timing_params()
75 writel(0xA100002, &mctl_ctl->dramtmg[13]); in mctl_set_timing_params()
[all …]
A Dh6_lpddr3.c88 &mctl_ctl->dramtmg[0]); in mctl_set_timing_params()
89 writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]); in mctl_set_timing_params()
91 &mctl_ctl->dramtmg[2]); in mctl_set_timing_params()
92 writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); in mctl_set_timing_params()
94 &mctl_ctl->dramtmg[4]); in mctl_set_timing_params()
96 &mctl_ctl->dramtmg[5]); in mctl_set_timing_params()
98 writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]); in mctl_set_timing_params()
100 &mctl_ctl->dramtmg[8]); in mctl_set_timing_params()
101 writel(txsr, &mctl_ctl->dramtmg[14]); in mctl_set_timing_params()
A Dh6_ddr3_1333.c100 &mctl_ctl->dramtmg[0]); in mctl_set_timing_params()
101 writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]); in mctl_set_timing_params()
103 &mctl_ctl->dramtmg[2]); in mctl_set_timing_params()
104 writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]); in mctl_set_timing_params()
106 &mctl_ctl->dramtmg[4]); in mctl_set_timing_params()
108 &mctl_ctl->dramtmg[5]); in mctl_set_timing_params()
110 writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]); in mctl_set_timing_params()
112 &mctl_ctl->dramtmg[8]); in mctl_set_timing_params()
113 writel(txsr, &mctl_ctl->dramtmg[14]); in mctl_set_timing_params()
A Dddr3_1333.c59 &mctl_ctl->dramtmg[0]); in mctl_set_timing_params()
61 &mctl_ctl->dramtmg[1]); in mctl_set_timing_params()
64 &mctl_ctl->dramtmg[2]); in mctl_set_timing_params()
66 &mctl_ctl->dramtmg[3]); in mctl_set_timing_params()
68 DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); in mctl_set_timing_params()
71 &mctl_ctl->dramtmg[5]); in mctl_set_timing_params()
74 clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), in mctl_set_timing_params()
A Dlpddr3_stock.c55 &mctl_ctl->dramtmg[0]); in mctl_set_timing_params()
57 &mctl_ctl->dramtmg[1]); in mctl_set_timing_params()
60 &mctl_ctl->dramtmg[2]); in mctl_set_timing_params()
62 &mctl_ctl->dramtmg[3]); in mctl_set_timing_params()
64 DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); in mctl_set_timing_params()
67 &mctl_ctl->dramtmg[5]); in mctl_set_timing_params()
70 clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), in mctl_set_timing_params()
A Dddr2_v3s.c56 &mctl_ctl->dramtmg[0]); in mctl_set_timing_params()
58 &mctl_ctl->dramtmg[1]); in mctl_set_timing_params()
61 &mctl_ctl->dramtmg[2]); in mctl_set_timing_params()
63 &mctl_ctl->dramtmg[3]); in mctl_set_timing_params()
65 DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); in mctl_set_timing_params()
68 &mctl_ctl->dramtmg[5]); in mctl_set_timing_params()
71 clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), in mctl_set_timing_params()
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun9i.c537 &mctl_ctl->dramtmg[0]); in mctl_channel_init()
540 &mctl_ctl->dramtmg[1]); in mctl_channel_init()
543 &mctl_ctl->dramtmg[2]); in mctl_channel_init()
549 &mctl_ctl->dramtmg[3]); in mctl_channel_init()
552 &mctl_ctl->dramtmg[4]); in mctl_channel_init()
555 &mctl_ctl->dramtmg[5]); in mctl_channel_init()
569 writel((MCTL_DIV32(tXSDLL) << 0), &mctl_ctl->dramtmg[8]); in mctl_channel_init()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Ddram_sun50i_h616.h86 u32 dramtmg[17]; /* 0x100 */ member
A Ddram_sunxi_dw.h93 u32 dramtmg[9]; /* 0x58 DRAM timing registers */ member
A Ddram_sun9i.h67 u32 dramtmg[9]; /* 0x100 DRAM timing register */ member
A Ddram_sun50i_h6.h101 u32 dramtmg[17]; /* 0x100 */ member

Completed in 16 milliseconds