Searched refs:dramtmg0 (Results 1 – 14 of 14) sorted by relevance
94 cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109; in cl_som_imx7_spl_dram_cfg_size()105 cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109; in cl_som_imx7_spl_dram_cfg_size()116 cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109; in cl_som_imx7_spl_dram_cfg_size()127 cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E110A; in cl_som_imx7_spl_dram_cfg_size()
44 .dramtmg0 = 0x09081109,61 .dramtmg0 = 0x09081109,
69 writel(ddrc_regs_val->dramtmg0, &ddrc_regs->dramtmg0); in mx7_dram_cfg()
32 u32 dramtmg0; /* 0x0100 */ member
88 u32 dramtmg0; /* 0x58 dram timing parameters register 0 */ member
120 u32 dramtmg0; /* 0x100 */ member
71 u32 dramtmg0; member
47 u32 dramtmg0; /* 0x100 SDRAM Timing 0*/ member
105 DDRCTL_REG_TIMING(dramtmg0),
160 &mctl_ctl->dramtmg0); in mctl_init()
141 writel(reg_val, &mctl_ctl->dramtmg0); in auto_set_timing_para()
173 writel(reg_val, &mctl_ctl->dramtmg0); in auto_set_timing_para()
34 u32 dramtmg0; member131 u32 dramtmg0; member
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