Searched refs:dramtmg5 (Results 1 – 14 of 14) sorted by relevance
49 .dramtmg5 = 0x03030202,
74 writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5); in mx7_dram_cfg()
50 .dramtmg5 = 0x03030202,
37 u32 dramtmg5; /* 0x0114 */ member
93 u32 dramtmg5; /* 0x6c dram timing parameters register 5 */ member
125 u32 dramtmg5; /* 0x114 */ member
76 u32 dramtmg5; member
52 u32 dramtmg5; /* 0x114 SDRAM Timing 5*/ member
110 DDRCTL_REG_TIMING(dramtmg5),
187 &mctl_ctl->dramtmg5); in mctl_init()
151 writel(reg_val, &mctl_ctl->dramtmg5); in auto_set_timing_para()
183 writel(reg_val, &mctl_ctl->dramtmg5); in auto_set_timing_para()
39 u32 dramtmg5; member136 u32 dramtmg5; member
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