Searched refs:dtpr2 (Results 1 – 17 of 17) sorted by relevance
| /u-boot/board/ti/ks2_evm/ |
| A D | ddr3_k2g.c | 29 .dtpr2 = 0x50022A00ul,
69 .dtpr2 = 0x50023600ul,
130 .dtpr2 = 0x50022A00ul,
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| A D | ddr3_cfg.c | 27 .dtpr2 = 0x5002D200ul,
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| /u-boot/arch/arm/mach-keystone/include/mach/ |
| A D | ddr3.h | 27 unsigned int dtpr2; member
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | sdram_rk3288.h | 78 u32 dtpr2; member
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| /u-boot/arch/arm/mach-keystone/ |
| A D | ddr3_spd.c | 34 debug_ddr_cfg("dtpr2 0x%08X\n", ptr->dtpr2); in dump_phy_config()
336 spd_cb->phy_cfg.dtpr2 = 0 << 31 | 1 << 30 | 0 << 29 | in init_ddr3param()
339 spd_cb->phy_cfg.dtpr2 |= (((spd->t_xp > spd->t_xpdll) ? in init_ddr3param()
343 spd_cb->phy_cfg.dtpr2 |= (((spd->t_xs > spd->t_xsdll) ? in init_ddr3param()
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| A D | ddr3.c | 54 __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); in ddr3_init_ddrphy()
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| /u-boot/board/imgtec/ci20/ |
| A D | ci20.c | 303 .dtpr2 = 0x10042a00,
347 .dtpr2 = 0x10042a00,
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| /u-boot/drivers/ram/stm32mp1/ |
| A D | stm32mp1_ddr.h | 136 u32 dtpr2; member
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| A D | stm32mp1_ddr_regs.h | 157 u32 dtpr2; /* 0x3C DRAM Timing Parameters2*/ member
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| A D | stm32mp1_ddr.c | 174 DDRPHY_REG_TIMING(dtpr2),
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| /u-boot/arch/mips/mach-jz47xx/jz4780/ |
| A D | sdram.c | 89 writel(ddr_config->dtpr2, ddr_phy_regs + DDRP_DTPR2); in ddr_phy_init()
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | dram_sun8i_a23.h | 183 u32 dtpr2; /* 0x50 dram timing parameters register 2 */ member
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| A D | dram_sun6i.h | 176 u32 dtpr2; /* 0x3c dram timing parameters register 2 */ member
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun8i_a23.c | 138 writel(dram_para.tpr4, &mctl_phy->dtpr2); in mctl_init()
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| A D | dram_sun6i.c | 146 (MCTL_TEXSR << 0), &mctl_phy->dtpr2); in mctl_channel_init()
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| /u-boot/arch/mips/mach-jz47xx/include/mach/ |
| A D | jz4780_dram.h | 447 u32 dtpr2; /* DRAM Timing Parameters Register 2 */ member
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| /u-boot/doc/device-tree-bindings/clock/ |
| A D | rockchip,rk3288-dmc.txt | 91 dtpr2
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