Home
last modified time | relevance | path

Searched refs:emif_rd_wr_lvl_rmp_ctl (Results 1 – 7 of 7) sorted by relevance

/u-boot/board/ti/dra7xx/
A Devm.c90 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
115 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
140 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
165 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
190 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
215 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
240 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
265 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
/u-boot/board/ti/am43xx/
A Dboard.c168 .emif_rd_wr_lvl_rmp_ctl = 0x0,
210 .emif_rd_wr_lvl_rmp_ctl = 0x0,
282 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
308 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
/u-boot/arch/arm/mach-omap2/omap5/
A Dsdram.c111 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
135 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
552 hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT; in do_ext_phy_settings_dra7()
/u-boot/arch/arm/mach-omap2/am33xx/
A Dddr.c98 writel(regs->emif_rd_wr_lvl_rmp_ctl, in config_sdram_emif4d5()
99 &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); in config_sdram_emif4d5()
153 writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl); in config_sdram_emif4d5()
/u-boot/arch/arm/mach-omap2/
A Demif-common.c298 writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl); in update_hwleveling_output()
437 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); in dra7_ddr3_init()
452 if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) { in dra7_ddr3_init()
502 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); in omap5_ddr3_init()
1502 writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl); in do_bug0039_workaround()
/u-boot/board/ti/am57xx/
A Dboard.c154 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
218 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
281 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
306 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
/u-boot/arch/arm/include/asm/
A Demif.h686 u32 emif_rd_wr_lvl_rmp_ctl; member
1230 u32 emif_rd_wr_lvl_rmp_ctl; member

Completed in 28 milliseconds