Searched refs:emif_sdram_ref_ctrl (Results 1 – 3 of 3) sorted by relevance
| /u-boot/arch/arm/mach-omap2/am33xx/ |
| A D | ddr.c | 125 clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl, in config_sdram_emif4d5()
134 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram_emif4d5()
189 writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* initially a large refresh period */ in config_sdram()
190 writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* trigger initialization */ in config_sdram()
191 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram()
199 writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram()
204 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram()
207 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram()
342 &emif_reg[nr]->emif_sdram_ref_ctrl); in config_ddr_phy()
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| /u-boot/arch/arm/mach-omap2/ |
| A D | emif-common.c | 142 setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); in lpddr2_init()
161 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); in lpddr2_init()
315 clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK, in dra7_ddr3_leveling()
330 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); in dra7_ddr3_leveling()
427 &emif->emif_sdram_ref_ctrl); in dra7_ddr3_init()
443 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); in dra7_ddr3_init()
450 writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); in dra7_ddr3_init()
481 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); in omap5_ddr3_init()
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| /u-boot/arch/arm/include/asm/ |
| A D | emif.h | 642 u32 emif_sdram_ref_ctrl; member
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