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Searched refs:emif_sdram_tim_1 (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/arm/mach-omap2/am33xx/
A Dddr.c222 writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1); in set_sdram_timings()
/u-boot/arch/arm/mach-omap2/
A Demif-common.c429 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); in dra7_ddr3_init()
492 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); in omap5_ddr3_init()
/u-boot/arch/arm/include/asm/
A Demif.h644 u32 emif_sdram_tim_1; member

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