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/u-boot/drivers/misc/
A Dali512x.c87 ali_write(0x30, enabled?1:0); in ali512x_set_fdc()
88 if (enabled) { in ali512x_set_fdc()
109 ali_write(0x30, enabled?1:0); in ali512x_set_pp()
110 if (enabled) { in ali512x_set_pp()
130 ali_write(0x30, enabled?1:0); in ali512x_set_uart()
131 if (enabled) { in ali512x_set_uart()
166 ali_write(0x30, enabled?1:0); in ali512x_set_rtc()
167 if (enabled) { in ali512x_set_rtc()
182 ali_write(0x30, enabled?1:0); in ali512x_set_kbc()
183 if (enabled) { in ali512x_set_kbc()
[all …]
A Dmisc_sandbox.c14 bool enabled; member
90 memcpy(rx_msg, &priv->enabled, sizeof(priv->enabled)); in misc_sandbox_call()
99 priv->enabled = !priv->enabled; in misc_sandbox_set_enabled()
116 priv->enabled = true; in misc_sandbox_probe()
/u-boot/test/dm/
A Dmisc.c20 bool enabled; in dm_test_misc() local
65 ut_assertok(misc_call(dev, 3, NULL, 0, &enabled, in dm_test_misc()
66 sizeof(enabled))); in dm_test_misc()
67 ut_asserteq(true, enabled); in dm_test_misc()
71 ut_assertok(misc_call(dev, 3, NULL, 0, &enabled, in dm_test_misc()
72 sizeof(enabled))); in dm_test_misc()
73 ut_asserteq(false, enabled); in dm_test_misc()
77 ut_assertok(misc_call(dev, 3, NULL, 0, &enabled, in dm_test_misc()
78 sizeof(enabled))); in dm_test_misc()
79 ut_asserteq(true, enabled); in dm_test_misc()
A Dscmi.c151 ut_assert(!scmi_ctx->agent[0]->clk[0].enabled); in dm_test_scmi_clocks()
152 ut_assert(!scmi_ctx->agent[0]->clk[1].enabled); in dm_test_scmi_clocks()
153 ut_assert(!scmi_ctx->agent[1]->clk[0].enabled); in dm_test_scmi_clocks()
158 ut_assert(!scmi_ctx->agent[0]->clk[0].enabled); in dm_test_scmi_clocks()
159 ut_assert(scmi_ctx->agent[0]->clk[1].enabled); in dm_test_scmi_clocks()
160 ut_assert(scmi_ctx->agent[1]->clk[0].enabled); in dm_test_scmi_clocks()
165 ut_assert(!scmi_ctx->agent[0]->clk[0].enabled); in dm_test_scmi_clocks()
166 ut_assert(!scmi_ctx->agent[0]->clk[1].enabled); in dm_test_scmi_clocks()
167 ut_assert(!scmi_ctx->agent[1]->clk[0].enabled); in dm_test_scmi_clocks()
/u-boot/include/
A Dali512x.h21 void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel);
22 void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel);
23 void ali512x_set_uart(int enabled, int index, u16 io, u8 irq);
24 void ali512x_set_rtc(int enabled, u16 io, u8 irq);
25 void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq);
26 void ali512x_set_cio(int enabled);
35 void ali512x_set_uart2_irda(int enabled);
/u-boot/drivers/net/ldpaa_eth/
A Dldpaa_wriop.c27 dpmac_info[dpmac_id].enabled = 0; in wriop_init_dpmac()
33 dpmac_info[dpmac_id].enabled = 1; in wriop_init_dpmac()
47 dpmac_info[dpmac_id].enabled = 1; in wriop_init_dpmac_enet_if()
77 dpmac_info[i].enabled = 0; in wriop_disable_dpmac()
90 dpmac_info[i].enabled = 1; in wriop_enable_dpmac()
103 return dpmac_info[i].enabled; in wriop_is_enabled_dpmac()
188 if (dpmac_info[i].enabled) in wriop_get_enet_if()
/u-boot/drivers/net/
A Dmdio_mux_sandbox.c16 int enabled; member
42 if (!priv->enabled) in mdio_mux_sandbox_select()
58 if (!priv->enabled) in mdio_mux_sandbox_deselect()
79 priv->enabled = 1; in mdio_mux_sandbox_probe()
A Dmdio_sandbox.c15 int enabled; member
23 if (!priv->enabled) in mdio_sandbox_read()
41 if (!priv->enabled) in mdio_sandbox_write()
77 priv->enabled = 1; in mdio_sandbox_probe()
/u-boot/drivers/dma/
A Dsandbox-dma-test.c28 bool enabled; member
124 if (uc->enabled) in sandbox_dma_enable()
127 uc->enabled = true; in sandbox_dma_enable()
128 debug("%s(dma id=%lu enabled=%d)\n", __func__, dma->id, uc->enabled); in sandbox_dma_enable()
144 if (!uc->enabled) in sandbox_dma_disable()
147 uc->enabled = false; in sandbox_dma_disable()
148 debug("%s(dma id=%lu enabled=%d)\n", __func__, dma->id, uc->enabled); in sandbox_dma_disable()
171 if (!uc->enabled) in sandbox_dma_send()
201 if (!uc->enabled) in sandbox_dma_receive()
266 uc->enabled = false; in sandbox_dma_probe()
/u-boot/arch/arm/mach-mvebu/
A Dmbus.c120 *enabled = 0; in mvebu_mbus_read_window()
124 *enabled = 1; in mvebu_mbus_read_window()
186 int enabled; in mvebu_mbus_window_conflicts() local
189 &enabled, &wbase, &wsize, in mvebu_mbus_window_conflicts()
192 if (!enabled) in mvebu_mbus_window_conflicts()
222 int enabled; in mvebu_mbus_find_window() local
225 &enabled, &wbase, &wsize, in mvebu_mbus_find_window()
228 if (!enabled) in mvebu_mbus_find_window()
426 int enabled; in mvebu_mbus_get_lowest_base() local
429 &enabled, &wbase, &wsize, in mvebu_mbus_get_lowest_base()
[all …]
/u-boot/board/LaCie/netspace_v2/
A Dkwbimage-is2.cfg36 # bit18: 1=cpu lock transaction enabled
75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
108 # bit7 : 1 , D2P Latency enabled
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
121 # bit0: 1, Window enabled
A Dkwbimage-ns2l.cfg36 # bit18: 1=cpu lock transaction enabled
75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
108 # bit7 : 1 , D2P Latency enabled
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
121 # bit0: 1, Window enabled
A Dkwbimage.cfg36 # bit18: 1=cpu lock transaction enabled
75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
108 # bit7 : 1 , D2P Latency enabled
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
121 # bit0: 1, Window enabled
/u-boot/board/LaCie/net2big_v2/
A Dkwbimage.cfg36 # bit18: 1=cpu lock transaction enabled
75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
95 # bit2: 1, DDR ODT control lsd enabled
97 # bit6: 1, DDR ODT control msb, enabled
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
108 # bit7 : 1 , D2P Latency enabled
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
121 # bit0: 1, Window enabled
/u-boot/drivers/net/fm/
A Dinit.c100 if ((fm_info[i].enabled) && (fm_info[i].index == 1)) in fm_standard_init()
110 if ((fm_info[i].enabled) && (fm_info[i].index == 2)) in fm_standard_init()
145 fm_info[i].enabled = 1; in fman_enet_init()
148 fm_info[i].enabled = 0; in fman_enet_init()
162 fm_info[i].enabled = 0; in fm_disable_port()
175 fm_info[i].enabled = 1; in fm_enable_port()
226 if (fm_info[i].enabled) in fm_info_get_enet_if()
257 if (info->enabled) { in ft_fixup_port()
/u-boot/arch/arm/dts/
A Drk3399pro.dtsi10 /* Default to enabled since AP talk to NPU part over pcie */
15 /* Default to enabled since AP talk to NPU part over pcie */
/u-boot/doc/
A DREADME.t1040-l2switch53 0 enabled down 10 half
54 1 enabled down 10 half
55 2 enabled down 10 half
56 3 enabled up 1000 full
61 8 enabled up 2500 full
62 9 enabled up 2500 full
/u-boot/drivers/video/
A Dpwm_backlight.c57 bool enabled; member
128 priv->enabled = true; in pwm_backlight_enable()
140 if (!priv->enabled) { in pwm_backlight_set_brightness()
166 if (!priv->enabled) { in pwm_backlight_set_brightness()
170 priv->enabled = true; in pwm_backlight_set_brightness()
179 priv->enabled = false; in pwm_backlight_set_brightness()
/u-boot/board/Marvell/sheevaplug/
A Dkwbimage.cfg35 # bit18: 1=cpu lock transaction enabled
75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
121 # bit0: 1, Window enabled
128 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
/u-boot/board/Marvell/dreamplug/
A Dkwbimage.cfg36 # bit18: 1=cpu lock transaction enabled
76 # bit0: 0, OpenPage enabled
94 # bit0: 0, DDR DLL enabled
100 # bit10: 0, differential DQS enabled
102 # bit12: 0, DDR output buffer enabled
112 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
122 # bit0: 1, Window enabled
129 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
/u-boot/board/Marvell/guruplug/
A Dkwbimage.cfg35 # bit18: 1=cpu lock transaction enabled
75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
121 # bit0: 1, Window enabled
128 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
/u-boot/drivers/clk/
A Dclk_sandbox.c16 bool enabled[SANDBOX_CLK_ID_COUNT]; member
79 priv->enabled[clk->id] = true; in sandbox_clk_enable()
94 priv->enabled[clk->id] = false; in sandbox_clk_disable()
170 return priv->enabled[id]; in sandbox_clk_query_enable()
/u-boot/board/Seagate/nas220/
A Dkwbimage.cfg40 # bit18: 1=cpu lock transaction enabled
80 # bit0: 0, OpenPage enabled
99 # bit0: 0, DDR DLL enabled
105 # bit10: 0, differential DQS enabled
107 # bit12: 0, DDR output buffer enabled
117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
123 # bit0: 1, Window enabled
/u-boot/common/
A Diotrace.c38 bool enabled; member
51 if (!(gd->flags & GD_FLG_RELOC) || !iotrace.enabled) in add_record()
161 iotrace.enabled = enable; in iotrace_set_enabled()
166 return iotrace.enabled; in iotrace_get_enabled()
/u-boot/board/Marvell/openrd/
A Dkwbimage.cfg35 # bit18: 1=cpu lock transaction enabled
75 # bit0: 0, OpenPage enabled
93 # bit0: 0, DDR DLL enabled
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
121 # bit0: 1, Window enabled
128 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1

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