Searched refs:ep0state (Results 1 – 9 of 9) sorted by relevance
128 ep0state = EP0_IDLE; in udc_write_urb()215 ep0state = EP0_IDLE; in udc_handle_ep0()220 ep0state = EP0_IDLE; in udc_handle_ep0()222 switch (ep0state) { in udc_handle_ep0()259 ep0state = EP0_IDLE; in udc_handle_ep0()323 ep0state = EP0_IDLE; in udc_handle_ep0()341 ep0state = EP0_IDLE; in udc_handle_ep0()350 ep0state = EP0_IDLE; in udc_handle_ep0()362 ep0state = EP0_IDLE; in udc_handle_ep0()417 ep0state = EP0_IDLE; in udc_irq()[all …]
45 dev->ep0state = WAIT_FOR_IN_COMPLETE; in dwc2_udc_ep0_zlp()319 dev->ep0state = WAIT_FOR_SETUP; in complete_tx()398 if (dev->ep0state == in process_ep_in_intr()454 } else if (dev->ep0state != in process_ep_out_intr()583 dev->ep0state = WAIT_FOR_SETUP; in dwc2_udc_irq()805 dev->ep0state = WAIT_FOR_SETUP; in dwc2_udc_ep0_set_stall()882 dev->ep0state = DATA_STATE_XMIT; in dwc2_ep0_write()1096 dev->ep0state = WAIT_FOR_SETUP; in dwc2_udc_set_halt()1338 dev->ep0state = WAIT_FOR_SETUP; in dwc2_ep0_setup()1349 dev->ep0state = WAIT_FOR_SETUP; in dwc2_ep0_setup()[all …]
80 int ep0state; member
106 if (dev->ep0state == EP0_STALL in udc_watchdog()164 state_name[dev->ep0state], in dump_state()444 dev->ep0state = EP0_IDLE; in ep0_idle()776 switch (dev->ep0state) { in pxa25x_ep_queue()794 dev->ep0state = EP0_END_XFER; in pxa25x_ep_queue()813 dev->ep0state); in pxa25x_ep_queue()929 ep->dev->ep0state = EP0_STALL; in pxa25x_ep_set_halt()1138 dev->ep0state = EP0_IDLE; in udc_reinit()1248 switch (dev->ep0state) { in handle_ep0()1331 dev->ep0state = EP0_IN_DATA_PHASE; in handle_ep0()[all …]
121 enum ep0_state ep0state; member
180 dev->ep0state = WAIT_FOR_SETUP; in udc_disable()199 dev->ep0state = WAIT_FOR_SETUP; in udc_reinit()
138 if (dwc->ep0state != EP0_DATA_PHASE) { in __dwc3_gadget_ep0_queue()162 if (dwc->ep0state == EP0_STATUS_PHASE) in __dwc3_gadget_ep0_queue()206 dwc->ep0state = EP0_DATA_PHASE; in __dwc3_gadget_ep0_queue()243 dwc3_ep0_state_string(dwc->ep0state)); in dwc3_gadget_ep0_queue()274 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_ep0_stall_and_restart()899 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_ep0_complete_status()912 switch (dwc->ep0state) { in dwc3_ep0_xfer_complete()928 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); in dwc3_ep0_xfer_complete()1078 dwc->ep0state = EP0_STATUS_PHASE; in dwc3_ep0_xfernotready()1098 dwc3_ep0_state_string(dwc->ep0state)); in dwc3_ep0_interrupt()
791 enum dwc3_ep0_state ep0state; member
1529 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_gadget_start()
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