| /u-boot/drivers/clk/analogbits/ |
| A D | wrpll-cln28hpc.c | 227 u8 fbdiv, divq, best_r, r; in wrpll_configure_for_rate() local
263 fbdiv = __wrpll_calc_fbdiv(c); in wrpll_configure_for_rate()
275 f >>= (fbdiv - 1); in wrpll_configure_for_rate()
278 vco_pre = fbdiv * post_divr_freq; in wrpll_configure_for_rate()
333 u8 fbdiv; in wrpll_calc_output_rate() local
341 fbdiv = __wrpll_calc_fbdiv(c); in wrpll_calc_output_rate()
342 n = parent_rate * fbdiv * (c->divf + 1); in wrpll_calc_output_rate()
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| /u-boot/drivers/clk/rockchip/ |
| A D | clk_rk3128.c | 53 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
65 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
82 u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0; in pll_para_config() local
118 fbdiv = vco_khz / fref_khz; in pll_para_config()
119 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) in pll_para_config()
121 diff_khz = vco_khz - fbdiv * fref_khz; in pll_para_config()
122 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { in pll_para_config()
123 fbdiv++; in pll_para_config()
132 div->fbdiv = fbdiv; in pll_para_config()
245 u32 refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
[all …]
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| A D | clk_pll.c | 131 rate_table->fbdiv = foutvco / clk_gcd; in rockchip_pll_clk_set_by_auto()
139 rate_table->fbdiv, rate_table->postdiv1, in rockchip_pll_clk_set_by_auto()
148 rate_table->fbdiv = foutvco / MHZ / clk_gcd; in rockchip_pll_clk_set_by_auto()
150 rate_table->refdiv, rate_table->fbdiv); in rockchip_pll_clk_set_by_auto()
196 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv); in rk3036_pll_set_rate()
216 rate->fbdiv); in rk3036_pll_set_rate()
254 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; in rk3036_pll_get_rate() local
270 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >> in rk3036_pll_get_rate()
282 rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rk3036_pll_get_rate()
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| A D | clk_rk322x.c | 36 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
54 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
58 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
70 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
179 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
206 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rkclk_pll_get_rate()
210 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
333 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
337 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
341 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
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| A D | clk_rk3036.c | 38 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
56 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
61 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
71 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
177 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
204 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rkclk_pll_get_rate()
208 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| A D | clk_rk3399.c | 42 u32 fbdiv; member
328 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
333 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
337 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
351 div->fbdiv << PLL_FBDIV_SHIFT); in rkclk_set_pll()
370 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_para_config() local
406 fbdiv = vco_khz / fref_khz; in pll_para_config()
407 if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv) in pll_para_config()
409 diff_khz = vco_khz - fbdiv * fref_khz; in pll_para_config()
411 fbdiv++; in pll_para_config()
[all …]
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| A D | clk_rk3328.c | 27 u32 fbdiv; member
39 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
246 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; in rkclk_set_pll()
251 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
255 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); in rkclk_set_pll()
269 (div->fbdiv << PLL_FBDIV_SHIFT) | in rkclk_set_pll()
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| A D | clk_px30.c | 40 .fbdiv = _fbdiv, \
101 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; in pll_clk_set_by_auto() local
137 fbdiv = vco_khz / fref_khz; in pll_clk_set_by_auto()
138 if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv) in pll_clk_set_by_auto()
141 diff_khz = vco_khz - fbdiv * fref_khz; in pll_clk_set_by_auto()
142 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { in pll_clk_set_by_auto()
143 fbdiv++; in pll_clk_set_by_auto()
152 rate->fbdiv = fbdiv; in pll_clk_set_by_auto()
224 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, in rkclk_set_pll()
264 u32 refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
[all …]
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| A D | clk_rv1108.c | 39 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
78 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; in rkclk_set_pll()
82 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
99 rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT); in rkclk_set_pll()
126 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
137 fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK; in rkclk_pll_get_rate()
141 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| /u-boot/drivers/video/rockchip/ |
| A D | rk_mipi.c | 201 u64 fbdiv; in rk_mipi_phy_enable() local
279 fbdiv = ddr_clk * prediv / refclk; in rk_mipi_phy_enable()
280 ddr_clk = refclk * fbdiv / prediv; in rk_mipi_phy_enable()
284 __func__, refclk, prediv, fbdiv, ddr_clk); in rk_mipi_phy_enable()
289 test_data[0] = (fbdiv - 1) & 0x1f; in rk_mipi_phy_enable()
291 test_data[0] = (fbdiv - 1) >> 5 | 0x80; in rk_mipi_phy_enable()
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | clock.h | 56 .fbdiv = _fbdiv, \
71 unsigned int fbdiv; member
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| A D | cru_rk3036.h | 60 u32 fbdiv; member
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| A D | cru_rk3128.h | 67 u32 fbdiv; member
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| A D | cru_rk322x.h | 61 u32 fbdiv; member
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| A D | cru_rv1108.h | 57 u32 fbdiv; member
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| A D | cru_px30.h | 102 unsigned int fbdiv; member
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| /u-boot/drivers/clk/ |
| A D | clk-hsdk-cgu.c | 196 const u8 fbdiv; member
404 val |= (u32)cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT; in hsdk_pll_set_cfg()
427 u32 idiv, fbdiv, odiv; in pll_get() local
446 fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT)); in pll_get()
450 rate = (u64)parent_rate * fbdiv; in pll_get()
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| A D | clk_versal.c | 385 u32 fbdiv; in versal_clock_get_pll_rate() local
403 fbdiv = ret_payload[1]; in versal_clock_get_pll_rate()
407 freq = (fbdiv * parent_rate) >> (1 << frac); in versal_clock_get_pll_rate()
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| /u-boot/drivers/ram/rockchip/ |
| A D | sdram_rk3328.c | 78 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
102 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
105 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]); in rkclk_set_dpll()
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| A D | sdram_px30.c | 156 unsigned int refdiv, postdiv1, postdiv2, fbdiv; in rkclk_set_dpll() local
180 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
184 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); in rkclk_set_dpll()
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| /u-boot/arch/arm/mach-rockchip/rk3036/ |
| A D | sdram_rk3036.c | 342 dpll_init_cfg.fbdiv); in rkdclk_init()
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