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/u-boot/drivers/clk/altera/
A Dclk-arria10.c33 u16 fix_div; member
152 rate /= plat->fix_div; in socfpga_a10_clk_get_rate()
154 if (plat->fix_div == 1 && plat->ctl_reg) { in socfpga_a10_clk_get_rate()
331 plat->fix_div = dev_read_u32_default(dev, "fixed-divider", 1); in socfpga_a10_of_to_plat()

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