1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2020 Cortina Access Inc.. 4 */ 5 6 /* Cortina NAND definition */ 7 #define NAND_BASE_ADDR 0xE0000000 8 #define BCH_GF_PARAM_M 14 9 #define BCH_DATA_UNIT 1024 10 #define FLASH_SHORT_DELAY 100 11 #define FLASH_LONG_DELAY 1000 12 #define FLASH_WIDTH 16 13 #define BBT_PAGE_MASK 0xffffff3f 14 #define WRITE_SIZE_512 512 15 #define WRITE_SIZE_2048 2048 16 #define WRITE_SIZE_4096 4096 17 #define WRITE_SIZE_8192 8192 18 #define ECC_STRENGTH_8 8 19 #define ECC_STRENGTH_16 16 20 #define ECC_STRENGTH_24 24 21 #define ECC_STRENGTH_40 40 22 #define EMPTY_PAGE 0xff 23 #define ADDR1_MASK0 0x00ffffff 24 #define ADDR2_MASK0 0xff000000 25 #define ADDR1_MASK1 0xffff 26 #define ADDR1_MASK2 0xff 27 #define OOB_MASK 0xff 28 #define EXT_ADDR_MASK 0x8000000 29 30 /* Status bits */ 31 #define NAND_STATUS_FAIL 0x01 32 #define NAND_STATUS_FAIL_N1 0x02 33 #define NAND_STATUS_TRUE_READY 0x20 34 #define NAND_STATUS_READY 0x40 35 #define NAND_STATUS_WP 0x80 36 37 /* Bit field in FLAS_TYPE */ 38 #define FLASH_PIN BIT(15) 39 #define FLASH_TYPE_512 0x4000 40 #define FLASH_TYPE_2K 0x5000 41 #define FLASH_TYPE_4K 0x6000 42 #define FLASH_TYPE_8K 0x7000 43 #define FLASH_SIZE_CONFIGURABLEOOB (0x0 << 9) 44 #define FLASH_SIZE_400OOB (0x1 << 9) 45 #define FLASH_SIZE_436OOB (0x2 << 9) 46 #define FLASH_SIZE_640OOB (0x3 << 9) 47 48 /* Bit field in FLASH_STATUS */ 49 #define NFLASH_READY BIT(26) 50 51 /* Bit field in FLASH_NF_ACCESS */ 52 #define NFLASH_ENABLE_ALTERNATIVE (0x0 << 15) 53 #define AUTO_RESET BIT(16) 54 #define DISABLE_AUTO_RESET (0x0 << 16) 55 #define NFLASH_REG_WIDTH_RESERVED (0x3 << 10) 56 #define NFLASH_REG_WIDTH_32 (0x2 << 10) 57 #define NFLASH_REG_WIDTH_16 (0x1 << 10) 58 #define NFLASH_REG_WIDTH_8 (0x0 << 10) 59 60 /* Bit field in FLASH_NF_COUNT */ 61 #define REG_CMD_COUNT_EMPTY 0x3 62 #define REG_CMD_COUNT_3TOGO 0x2 63 #define REG_CMD_COUNT_2TOGO 0x1 64 #define REG_CMD_COUNT_1TOGO 0x0 65 #define REG_ADDR_COUNT_EMPTY (0x7 << 4) 66 #define REG_ADDR_COUNT_5 (0x4 << 4) 67 #define REG_ADDR_COUNT_4 (0x3 << 4) 68 #define REG_ADDR_COUNT_3 (0x2 << 4) 69 #define REG_ADDR_COUNT_2 (0x1 << 4) 70 #define REG_ADDR_COUNT_1 (0x0 << 4) 71 #define REG_DATA_COUNT_EMPTY (0x3fff << 8) 72 #define REG_DATA_COUNT_512_DATA (0x1FF << 8) 73 #define REG_DATA_COUNT_2k_DATA (0x7FF << 8) 74 #define REG_DATA_COUNT_4k_DATA (0xFFF << 8) 75 #define REG_DATA_COUNT_DATA_1 (0x0 << 8) 76 #define REG_DATA_COUNT_DATA_2 (0x1 << 8) 77 #define REG_DATA_COUNT_DATA_3 (0x2 << 8) 78 #define REG_DATA_COUNT_DATA_4 (0x3 << 8) 79 #define REG_DATA_COUNT_DATA_5 (0x4 << 8) 80 #define REG_DATA_COUNT_DATA_6 (0x5 << 8) 81 #define REG_DATA_COUNT_DATA_7 (0x6 << 8) 82 #define REG_DATA_COUNT_DATA_8 (0x7 << 8) 83 #define REG_OOB_COUNT_EMPTY (0x3ff << 22) 84 85 /* Bit field in FLASH_FLASH_ACCESS_START */ 86 #define NFLASH_GO BIT(0) 87 #define NFLASH_FIFO_REQ BIT(2) 88 #define NFLASH_RD BIT(13) 89 #define NFLASH_WT (BIT(12) | BIT(13)) 90 91 /* Bit field in FLASH_NF_ECC_RESET */ 92 #define RESET_NFLASH_RESET BIT(2) 93 #define RESET_NFLASH_FIFO BIT(1) 94 #define RESET_NFLASH_ECC BIT(0) 95 #define ECC_RESET_ALL \ 96 RESET_NFLASH_RESET | RESET_NFLASH_FIFO | RESET_NFLASH_ECC 97 98 /* Bit field in FLASH_NF_ECC_CONTROL */ 99 #define ENABLE_ECC_GENERATION BIT(8) 100 #define DISABLE_ECC_GENERATION (0 << 8) 101 102 /* Flash FIFO control */ 103 #define FIFO_READ 2 104 #define FIFO_WRITE 3 105 106 /* NFLASH INTERRUPT */ 107 #define REGIRQ_CLEAR BIT(0) 108 #define F_ADDR_ERR 2 109 110 /* BCH ECC field definition */ 111 #define BCH_COMPARE BIT(0) 112 #define BCH_ENABLE BIT(8) 113 #define BCH_DISABLE (0 << 8) 114 #define BCH_DECODE BIT(1) 115 #define BCH_ENCODE (0 << 1) 116 #define BCH_DECO_DONE BIT(30) 117 #define BCH_GEN_DONE BIT(31) 118 #define BCH_UNCORRECTABLE 0x3 119 #define BCH_CORRECTABLE_ERR 0x2 120 #define BCH_NO_ERR 0x1 121 #define BCH_BUSY 0x0 122 #define BCH_ERR_MASK 0x3 123 #define BCH_ERR_NUM_MASK 0x3F 124 #define BCH_ERR_LOC_MASK 0x3FFF 125 #define BCH_CORRECT_LOC_MASK 0x7 126 #define BCH_ERR_CAP_8 (0x0 << 9) 127 #define BCH_ERR_CAP_16 (0x1 << 9) 128 #define BCH_ERR_CAP_24 (0x2 << 9) 129 #define BCH_ERR_CAP_40 (0x3 << 9) 130 131 #define BCH_GF_PARAM_M 14 132 133 struct nand_ctlr { 134 /* Cortina NAND controller register */ 135 u32 flash_id; 136 u32 flash_timeout; 137 u32 flash_status; 138 u32 flash_type; 139 u32 flash_flash_access_start; 140 u32 flash_flash_interrupt; 141 u32 flash_flash_mask; 142 u32 flash_fifo_control; 143 u32 flash_fifo_status; 144 u32 flash_fifo_address; 145 u32 flash_fifo_match_address; 146 u32 flash_fifo_data; 147 u32 flash_sf_access; 148 u32 flash_sf_ext_access; 149 u32 flash_sf_address; 150 u32 flash_sf_data; 151 u32 flash_sf_timing; 152 u32 resv[3]; 153 u32 flash_pf_access; // offset 0x050 154 u32 flash_pf_timing; 155 u32 resv1[2]; 156 u32 flash_nf_access; // offset 0x060 157 u32 flash_nf_count; 158 u32 flash_nf_command; 159 u32 flash_nf_address_1; 160 u32 flash_nf_address_2; 161 u32 flash_nf_data; 162 u32 flash_nf_timing; 163 u32 flash_nf_ecc_status; 164 u32 flash_nf_ecc_control; 165 u32 flash_nf_ecc_oob; 166 u32 flash_nf_ecc_gen0; 167 u32 resv3[15]; 168 u32 flash_nf_ecc_reset; // offset 0x0c8 169 u32 flash_nf_bch_control; 170 u32 flash_nf_bch_status; 171 u32 flash_nf_bch_error_loc01; 172 u32 resv4[19]; 173 u32 flash_nf_bch_oob0; // offset 0x124 174 u32 resv5[17]; 175 u32 flash_nf_bch_gen0_0; // offset 0x16c 176 }; 177 178 /* Definition for DMA bitfield */ 179 #define TX_DMA_ENABLE BIT(0) 180 #define RX_DMA_ENABLE BIT(0) 181 #define DMA_CHECK_OWNER BIT(1) 182 #define OWN_DMA 0 183 #define OWN_CPU 1 184 185 #define CA_DMA_DEPTH 3 186 #define CA_DMA_DESC_NUM (BIT(0) << CA_DMA_DEPTH) 187 #define CA_DMA_Q_PTR_MASK 0x1fff 188 189 struct dma_q_base_depth_t { 190 u32 depth : 4 ; /* bits 3:0 */ 191 u32 base : 28 ; /* bits 31:4 */ 192 }; 193 194 struct tx_descriptor_t { 195 unsigned int buf_adr; /* Buff addr */ 196 unsigned int buf_adr_hi : 8 ; /* bits 7:0 */ 197 unsigned int buf_len : 16 ; /* bits 23:8 */ 198 unsigned int sgm : 1 ; /* bits 24 */ 199 unsigned int rsrvd : 6 ; /* bits 30:25 */ 200 unsigned int own : 1 ; /* bits 31:31 */ 201 }; 202 203 struct rx_descriptor_t { 204 unsigned int buf_adr; /* Buff addr */ 205 unsigned int buf_adr_hi : 8 ; /* bits 7:0 */ 206 unsigned int buf_len : 16 ; /* bits 23:8 */ 207 unsigned int rsrvd : 7 ; /* bits 30:24 */ 208 unsigned int own : 1 ; /* bits 31:31 */ 209 }; 210 211 struct dma_global { 212 u32 dma_glb_dma_lso_ctrl; 213 u32 dma_glb_lso_interrupt; 214 u32 dma_glb_lso_intenable; 215 u32 dma_glb_dma_lso_vlan_tag_type0; 216 u32 dma_glb_dma_lso_vlan_tag_type1; 217 u32 dma_glb_dma_lso_axi_user_sel0; 218 u32 dma_glb_axi_user_pat0; 219 u32 dma_glb_axi_user_pat1; 220 u32 dma_glb_axi_user_pat2; 221 u32 dma_glb_axi_user_pat3; 222 u32 dma_glb_fast_reg_pe0; 223 u32 dma_glb_fast_reg_pe1; 224 u32 dma_glb_dma_lso_tx_fdes_addr0; 225 u32 dma_glb_dma_lso_tx_fdes_addr1; 226 u32 dma_glb_dma_lso_tx_cdes_addr0; 227 u32 dma_glb_dma_lso_tx_cdes_addr1; 228 u32 dma_glb_dma_lso_tx_des_word0; 229 u32 dma_glb_dma_lso_tx_des_word1; 230 u32 dma_glb_dma_lso_lso_para_word0; 231 u32 dma_glb_dma_lso_lso_para_word1; 232 u32 dma_glb_dma_lso_debug0; 233 u32 dma_glb_dma_lso_debug1; 234 u32 dma_glb_dma_lso_debug2; 235 u32 dma_glb_dma_lso_spare0; 236 u32 dma_glb_dma_lso_spare1; 237 u32 dma_glb_dma_ssp_rx_ctrl; 238 u32 dma_glb_dma_ssp_tx_ctrl; 239 u32 dma_glb_dma_ssp_axi_user_sel0; 240 u32 dma_glb_dma_ssp_axi_user_sel1; 241 u32 dma_glb_dma_ssp_rx_fdes_addr0; 242 u32 dma_glb_dma_ssp_rx_fdes_addr1; 243 u32 dma_glb_dma_ssp_rx_cdes_addr0; 244 u32 dma_glb_dma_ssp_rx_cdes_addr1; 245 u32 dma_glb_dma_ssp_rx_des_word0; 246 u32 dma_glb_dma_ssp_rx_des_word1; 247 u32 dma_glb_dma_ssp_tx_fdes_addr0; 248 u32 dma_glb_dma_ssp_tx_fdes_addr1; 249 u32 dma_glb_dma_ssp_tx_cdes_addr0; 250 u32 dma_glb_dma_ssp_tx_cdes_addr1; 251 u32 dma_glb_dma_ssp_tx_des_word0; 252 u32 dma_glb_dma_ssp_tx_des_word1; 253 u32 dma_glb_dma_ssp_debug0; 254 u32 dma_glb_dma_ssp_debug1; 255 u32 dma_glb_dma_ssp_debug2; 256 u32 dma_glb_dma_ssp_spare0; 257 u32 dma_glb_dma_ssp_spare1; 258 }; 259 260 struct dma_ssp { 261 u32 dma_q_rxq_control; 262 u32 dma_q_rxq_base_depth; 263 u32 dma_q_rxq_base; 264 u32 dma_q_rxq_wptr; 265 u32 dma_q_rxq_rptr; 266 u32 dma_q_rxq_pktcnt; 267 u32 dma_q_txq_control; 268 u32 dma_q_txq_base_depth; 269 u32 dma_q_txq_base; 270 u32 dma_q_txq_wptr; 271 u32 dma_q_txq_rptr; 272 u32 dma_q_txq_pktcnt; 273 u32 dma_q_rxq_interrupt; 274 u32 dma_q_rxq_intenable; 275 u32 dma_q_txq_interrupt; 276 u32 dma_q_txq_intenable; 277 u32 dma_q_rxq_misc_interrupt; 278 u32 dma_q_rxq_misc_intenable; 279 u32 dma_q_txq_misc_interrupt; 280 u32 dma_q_txq_misc_intenable; 281 u32 dma_q_rxq_coal_interrupt; 282 u32 dma_q_rxq_coal_intenable; 283 u32 dma_q_txq_coal_interrupt; 284 u32 dma_q_txq_coal_intenable; 285 u32 dma_q_rxq_frag_buff_addr0; 286 u32 dma_q_rxq_frag_buff_addr1; 287 u32 dma_q_rxq_frag_buff_size; 288 u32 dma_q_txq_frag_buff_addr0; 289 u32 dma_q_txq_frag_buff_addr1; 290 u32 dma_q_txq_frag_buff_size; 291 u32 dma_q_dma_spare_0; 292 u32 dma_q_dma_spare_1; 293 }; 294