| /u-boot/drivers/clk/imx/ |
| A D | clk-pfd.c | 49 u8 frac = (readl(pfd->reg) >> (pfd->idx * 8)) & 0x3f; in clk_pfd_recalc_rate() local
52 do_div(tmp, frac); in clk_pfd_recalc_rate()
62 u8 frac; in clk_pfd_set_rate() local
66 frac = tmp; in clk_pfd_set_rate()
67 if (frac < 12) in clk_pfd_set_rate()
68 frac = 12; in clk_pfd_set_rate()
69 else if (frac > 35) in clk_pfd_set_rate()
70 frac = 35; in clk_pfd_set_rate()
73 writel(frac << (pfd->idx * 8), pfd->reg + SET); in clk_pfd_set_rate()
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| /u-boot/drivers/video/meson/ |
| A D | meson_vclk.c | 435 if (frac) in meson_hdmi_pll_set_params()
437 0x00004000 | frac); in meson_hdmi_pll_set_params()
482 if (frac < 0x10000) { in meson_hdmi_pll_set_params()
574 unsigned int frac; in meson_hdmi_pll_get_frac() local
592 if (frac_m > frac) in meson_hdmi_pll_get_frac()
594 frac -= frac_m; in meson_hdmi_pll_get_frac()
601 unsigned int frac) in meson_hdmi_pll_validate_params() argument
630 unsigned int *frac, in meson_hdmi_pll_find_params() argument
641 freq, *m, *frac, *od); in meson_hdmi_pll_find_params()
654 unsigned int od, m, frac; in meson_vclk_dmt_supported_freq() local
[all …]
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| /u-boot/drivers/phy/ |
| A D | phy-stm32-usbphyc.c | 54 u16 frac; member
73 unsigned long long fvco, ndiv, frac; in stm32_usbphyc_get_pll_params() local
90 frac = fvco * (1 << 16); in stm32_usbphyc_get_pll_params()
91 do_div(frac, (clk_rate * 2)); in stm32_usbphyc_get_pll_params()
92 frac = frac - (ndiv * (1 << 16)); in stm32_usbphyc_get_pll_params()
93 pll_params->frac = (u16)frac; in stm32_usbphyc_get_pll_params()
113 if (pll_params.frac) { in stm32_usbphyc_pll_init()
115 usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT) in stm32_usbphyc_pll_init()
122 clk_rate, pll_params.ndiv, pll_params.frac); in stm32_usbphyc_pll_init()
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| /u-boot/drivers/pwm/ |
| A D | pwm-sifive.c | 67 u32 scale, val = 0, frac; in pwm_sifive_set_config() local
89 frac = DIV_ROUND_CLOSEST_ULL(num, period_ns); in pwm_sifive_set_config()
90 frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1); in pwm_sifive_set_config()
93 writel(frac, priv->base + regs->cmp0 + channel * in pwm_sifive_set_config()
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| /u-boot/drivers/clk/rockchip/ |
| A D | clk_pll.c | 133 rate_table->frac = 0; in rockchip_pll_clk_set_by_auto()
152 rate_table->frac = 0; in rockchip_pll_clk_set_by_auto()
159 rate_table->frac = frac_64; in rockchip_pll_clk_set_by_auto()
160 if (rate_table->frac > 0) in rockchip_pll_clk_set_by_auto()
162 debug("frac = %x\n", rate_table->frac); in rockchip_pll_clk_set_by_auto()
198 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac); in rk3036_pll_set_rate()
228 (rate->frac << RK3036_PLLCON2_FRAC_SHIFT), in rk3036_pll_set_rate()
254 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; in rk3036_pll_get_rate() local
280 frac = (con & RK3036_PLLCON2_FRAC_MASK) >> in rk3036_pll_get_rate()
284 u64 frac_rate = OSC_HZ * (u64)frac; in rk3036_pll_get_rate()
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| /u-boot/arch/arm/cpu/arm926ejs/mxs/ |
| A D | clock.c | 43 uint8_t clkfrac, frac; in mxs_get_pclk() local
64 frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; in mxs_get_pclk()
66 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; in mxs_get_pclk()
93 uint8_t clkfrac, frac; in mxs_get_emiclk() local
107 frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; in mxs_get_emiclk()
109 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; in mxs_get_emiclk()
124 uint8_t clkfrac, frac; in mxs_get_gpmiclk() local
137 frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK; in mxs_get_gpmiclk()
139 return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; in mxs_get_gpmiclk()
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| /u-boot/drivers/clk/ |
| A D | clk_pic32.c | 178 u64 frac; in pic32_set_refclk() local
190 frac = parent_rate; in pic32_set_refclk()
191 frac <<= 8; in pic32_set_refclk()
192 do_div(frac, rate); in pic32_set_refclk()
193 frac -= (u64)(div << 9); in pic32_set_refclk()
194 trim = (frac >= REFO_TRIM_MAX) ? REFO_TRIM_MAX : (u32)frac; in pic32_set_refclk()
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| A D | clk_versal.c | 387 u32 frac; in versal_clock_get_pll_rate() local
405 frac = ret_payload[1]; in versal_clock_get_pll_rate()
407 freq = (fbdiv * parent_rate) >> (1 << frac); in versal_clock_get_pll_rate()
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| /u-boot/arch/arm/mach-imx/mx7ulp/ |
| A D | pcc.c | 161 int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div) in pcc_clock_div_config() argument
166 (div == 1 && frac != 0)) in pcc_clock_div_config()
184 if (frac) in pcc_clock_div_config()
256 u32 reg, val, rate, frac, div; in pcc_clock_get_rate() local
272 frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET; in pcc_clock_get_rate()
279 rate = rate * (frac + 1) / (div + 1); in pcc_clock_get_rate()
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| A D | scg.c | 631 int scg_enable_pll_pfd(enum scg_clk clk, u32 frac) in scg_enable_pll_pfd() argument
637 if (frac < 12 || frac > 35) in scg_enable_pll_pfd()
700 reg |= (frac << shift) & mask; in scg_enable_pll_pfd()
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| /u-boot/arch/arm/mach-imx/mx7/ |
| A D | clock.c | 188 u32 freq, div, frac; in mxc_get_pll_sys_derive() local
215 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >> in mxc_get_pll_sys_derive()
222 frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >> in mxc_get_pll_sys_derive()
230 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >> in mxc_get_pll_sys_derive()
237 frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >> in mxc_get_pll_sys_derive()
245 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >> in mxc_get_pll_sys_derive()
252 frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >> in mxc_get_pll_sys_derive()
260 frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >> in mxc_get_pll_sys_derive()
267 frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >> in mxc_get_pll_sys_derive()
274 frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >> in mxc_get_pll_sys_derive()
[all …]
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | clock.h | 61 .frac = _frac, \
76 unsigned int frac; member
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| A D | cru_rk3036.h | 63 u32 frac; member
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| A D | cru_rk3128.h | 70 u32 frac; member
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| A D | cru_rk322x.h | 64 u32 frac; member
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| A D | cru_rv1108.h | 60 u32 frac; member
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| /u-boot/arch/mips/mach-ath79/qca953x/ |
| A D | lowlevel_init.S | 37 #define MK_PLL_CPU_CONF(frac, nint, ref, outdiv) \ argument
38 (PLL_CPU_NFRAC(frac) | \
47 #define MK_PLL_DDR_CONF(frac, nint, ref, outdiv) \ argument
48 (PLL_DDR_NFRAC(frac) | \
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| /u-boot/arch/arm/dts/ |
| A D | stm32mp157c-odyssey-som-u-boot.dtsi | 105 frac = < 0x1400 >;
114 frac = < 0x1a04 >;
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| A D | stm32mp15xx-dhcor-u-boot.dtsi | 143 frac = < 0x1400 >;
152 frac = < 0x1a04 >;
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| A D | stm32mp157a-dk1-u-boot.dtsi | 142 frac = < 0x1400 >;
151 frac = < 0x1a04 >;
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| A D | stm32mp157c-ed1-u-boot.dtsi | 138 frac = < 0x1400 >;
147 frac = < 0x1a04 >;
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| A D | stm32mp15xx-dhcom-u-boot.dtsi | 204 frac = < 0x1400 >;
213 frac = < 0x1a04 >;
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| /u-boot/doc/device-tree-bindings/clock/ |
| A D | st,stm32h7-rcc.txt | 57 st,frac-status = <0>;
58 st,frac = <0>;
97 - st,frac-status:
101 - st,frac: Fractional part of the multiplication factor : <0..8191>
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| A D | st,stm32mp1.txt | 116 - frac : Fractional part of the multiplication factor
134 frac = < 0x810 >;
373 frac = < 0x800 >;
383 frac = < 0x1400 >;
392 frac = < 0x1a04 >;
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| /u-boot/drivers/clk/at91/ |
| A D | clk-sam9x60-pll.c | 59 static long sam9x60_frac_pll_compute_mul_frac(u32 *mul, u32 *frac, ulong rate, in sam9x60_frac_pll_compute_mul_frac() argument
90 *frac = nfrac; in sam9x60_frac_pll_compute_mul_frac()
145 u32 mul, frac, val; in sam9x60_frac_pll_get_rate() local
154 frac = (val & pll->layout->frac_mask) >> pll->layout->frac_shift; in sam9x60_frac_pll_get_rate()
156 return (parent_rate * (mul + 1) + ((u64)parent_rate * frac >> 22)); in sam9x60_frac_pll_get_rate()
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