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Searched refs:freq (Results 1 – 25 of 253) sorted by relevance

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/u-boot/arch/arm/cpu/armv7/ls102xa/
A Dtimer.c37 unsigned long freq; in tick_to_time() local
39 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); in tick_to_time()
42 do_div(tick, freq); in tick_to_time()
49 unsigned long freq; in us_to_tick() local
51 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); in us_to_tick()
53 usec = usec * freq + 999999; in us_to_tick()
62 unsigned long ctrl, freq; in timer_init() local
68 freq = COUNTER_FREQUENCY; in timer_init()
69 asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); in timer_init()
121 unsigned long freq; in get_tbclk() local
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/u-boot/arch/arm/mach-imx/
A Dsyscounter.c40 unsigned long freq; in tick_to_time() local
42 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); in tick_to_time()
45 do_div(tick, freq); in tick_to_time()
52 unsigned long freq; in us_to_tick() local
54 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); in us_to_tick()
56 usec = usec * freq + 999999; in us_to_tick()
66 unsigned long val, freq; in timer_init() local
68 freq = CONFIG_SC_TIMER_CLK; in timer_init()
71 writel(freq, &sctr->cntfid0); in timer_init()
121 unsigned long freq; in get_tbclk() local
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/u-boot/arch/arm/cpu/armv8/s32v234/
A Dgeneric.c102 u32 freq = 0; in get_mcu_main_clk() local
114 freq = FIRC_CLK_FREQ; in get_mcu_main_clk()
117 freq = XOSC_CLK_FREQ; in get_mcu_main_clk()
137 u32 freq = 0; in get_sys_clk() local
161 freq = FIRC_CLK_FREQ; in get_sys_clk()
164 freq = XOSC_CLK_FREQ; in get_sys_clk()
183 u32 freq = 0; in get_peripherals_clk() local
213 freq = FIRC_CLK_FREQ; in get_uart_clk()
216 freq = XOSC_CLK_FREQ; in get_uart_clk()
234 u32 freq = 0; in get_fec_clk() local
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/u-boot/arch/arm/cpu/armv7/vf610/
A Dgeneric.c51 u32 freq = 0; in get_mcu_main_clk() local
64 freq = FASE_CLK_FREQ; in get_mcu_main_clk()
67 freq = SLOW_CLK_FREQ; in get_mcu_main_clk()
73 freq = PLL2_MAIN_FREQ; in get_mcu_main_clk()
75 freq = PLL2_PFD1_FREQ; in get_mcu_main_clk()
84 freq = PLL2_MAIN_FREQ; in get_mcu_main_clk()
101 freq = PLL3_MAIN_FREQ; in get_mcu_main_clk()
147 u32 freq = 0; in get_sdhc_clk() local
169 freq = get_bus_clk(); in get_sdhc_clk()
180 u32 freq = 0; in get_fec_clk() local
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/u-boot/arch/arm/mach-imx/imx8m/
A Dclock_imx8mq.c369 void mxs_set_lcdclk(u32 base_addr, u32 freq) in mxs_set_lcdclk() argument
763 u32 freq; in do_imx8m_showclocks() local
765 freq = decode_frac_pll(ARM_PLL_CLK); in do_imx8m_showclocks()
767 freq = decode_sscg_pll(DRAM_PLL1_CLK); in do_imx8m_showclocks()
783 freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK); in do_imx8m_showclocks()
785 freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK); in do_imx8m_showclocks()
803 freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK); in do_imx8m_showclocks()
805 freq = decode_sscg_pll(SYSTEM_PLL3_CLK); in do_imx8m_showclocks()
807 freq = mxc_get_clock(UART1_CLK_ROOT); in do_imx8m_showclocks()
809 freq = mxc_get_clock(USDHC1_CLK_ROOT); in do_imx8m_showclocks()
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/u-boot/arch/arm/mach-at91/armv7/
A Dclock.c48 freq /= div; in at91_pll_rate()
49 freq *= mul + 1; in at91_pll_rate()
51 freq = 0; in at91_pll_rate()
54 return freq; in at91_pll_rate()
59 unsigned freq, mckr; in at91_clock_init() local
93 freq = gd->arch.mck_rate_hz; in at91_clock_init()
263 u32 freq; in at91_get_periph_generated_clk() local
280 freq = gd->arch.plla_rate_hz; in at91_get_periph_generated_clk()
286 freq = gd->arch.mck_rate_hz; in at91_get_periph_generated_clk()
290 freq = 0; in at91_get_periph_generated_clk()
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/u-boot/arch/arm/mach-imx/mx5/
A Dclock.c256 u32 reg, freq; in get_mcu_main_clk() local
294 freq = get_ahb_clk(); in get_ipg_clk()
299 return freq / div; in get_ipg_clk()
313 freq = get_lp_apm(); in get_ipg_per_clk()
326 u32 freq = 0; in get_standard_pll_sel_clk() local
339 freq = get_lp_apm(); in get_standard_pll_sel_clk()
343 return freq; in get_standard_pll_sel_clk()
362 return freq; in get_uart_clk()
417 return freq; in get_esdhc_clk()
890 freq *= SZ_DEC_1M; in mxc_set_clock()
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/u-boot/arch/arm/mach-keystone/
A Dclock.c346 unsigned long freq = 0; in ks_clk_get_rate() local
350 freq = pll_freq_get(CORE_PLL); in ks_clk_get_rate()
353 freq = pll_freq_get(PASS_PLL); in ks_clk_get_rate()
357 freq = pll_freq_get(TETRIS_PLL); in ks_clk_get_rate()
360 freq = pll_freq_get(DDR3A_PLL); in ks_clk_get_rate()
364 freq = pll_freq_get(DDR3B_PLL); in ks_clk_get_rate()
368 freq = pll_freq_get(UART_PLL); in ks_clk_get_rate()
384 freq = ks_clk_get_rate(sys_clk0_clk) / 2; in ks_clk_get_rate()
387 freq = ks_clk_get_rate(sys_clk0_clk) / 3; in ks_clk_get_rate()
390 freq = ks_clk_get_rate(sys_clk0_clk) / 4; in ks_clk_get_rate()
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/u-boot/arch/arm/mach-at91/arm926ejs/
A Dclock.c99 static u32 at91_pll_rate(u32 freq, u32 reg) in at91_pll_rate() argument
106 freq /= div; in at91_pll_rate()
107 freq *= mul + 1; in at91_pll_rate()
109 freq = 0; in at91_pll_rate()
111 return freq; in at91_pll_rate()
116 unsigned freq, mckr; in at91_clock_init() local
163 freq = gd->arch.mck_rate_hz; in at91_clock_init()
175 freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; in at91_clock_init()
188 ? freq / 3 in at91_clock_init()
191 gd->arch.mck_rate_hz = freq / in at91_clock_init()
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/u-boot/arch/arm/mach-at91/arm920t/
A Dclock.c91 static u32 at91_pll_rate(u32 freq, u32 reg) in at91_pll_rate() argument
98 freq /= div; in at91_pll_rate()
99 freq *= mul + 1; in at91_pll_rate()
101 freq = 0; in at91_pll_rate()
103 return freq; in at91_pll_rate()
108 unsigned freq, mckr; in at91_clock_init() local
150 freq = gd->arch.mck_rate_hz; in at91_clock_init()
152 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ in at91_clock_init()
154 gd->arch.mck_rate_hz = freq / in at91_clock_init()
156 gd->arch.cpu_clk_rate_hz = freq; in at91_clock_init()
/u-boot/drivers/misc/
A Dk3_avs.c36 u32 freq; member
169 if (opp->freq == freq) in match_opp()
203 opp_id = match_opp(vd, freq); in k3_avs_notify_freq()
280 if (!opp->freq) in k3_avs_probe()
321 .freq = 800000000,
325 .freq = 1000000000,
329 .freq = 1100000000,
341 .freq = 800000000,
345 .freq = 1000000000,
349 .freq = 1100000000,
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/u-boot/arch/arm/mach-uniphier/dram/
A Dumc-pxs2.c162 tmp = ddrphy_pgcr2[freq]; in ddrphy_init()
167 writel(ddrphy_ptr0[freq], phy_base + MPHY_PTR0); in ddrphy_init()
188 writel(ddrphy_mr0[freq], phy_base + MPHY_MR0); in ddrphy_init()
190 writel(ddrphy_mr2[freq], phy_base + MPHY_MR2); in ddrphy_init()
489 writel(ch == 2 ? umc_cmdctlb_ch2[freq] : umc_cmdctlb_ch01[freq], in umc_dc_init()
520 writel(ch == 2 ? umc_flowctla_ch2[freq] : umc_flowctla_ch01[freq], in umc_dc_init()
559 ddrphy_init(phy_base, freq, width, ch); in umc_ch_init()
609 enum dram_freq freq; in uniphier_pxs2_umc_init() local
614 freq = DRAM_FREQ_1866M; in uniphier_pxs2_umc_init()
617 freq = DRAM_FREQ_2133M; in uniphier_pxs2_umc_init()
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/u-boot/drivers/ddr/marvell/a38x/
A Dmv_ddr_plat.c408 *freq = MV_DDR_FREQ_333; in mv_ddr_sar_freq_get()
416 *freq = MV_DDR_FREQ_400; in mv_ddr_sar_freq_get()
424 *freq = MV_DDR_FREQ_533; in mv_ddr_sar_freq_get()
427 *freq = MV_DDR_FREQ_600; in mv_ddr_sar_freq_get()
436 *freq = MV_DDR_FREQ_667; in mv_ddr_sar_freq_get()
457 *freq = 0; in mv_ddr_sar_freq_get()
475 *freq = 0; in mv_ddr_sar_freq_get()
532 *freq = 0; in ddr3_tip_a38x_get_medium_freq()
552 *freq = 0; in ddr3_tip_a38x_get_medium_freq()
929 enum mv_ddr_freq freq; in mv_ddr_init_freq_get() local
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/u-boot/arch/arm/mach-imx/mx7/
A Dclock.c200 return freq; in mxc_get_pll_sys_derive()
205 return freq / 2; in mxc_get_pll_sys_derive()
210 return freq / 4; in mxc_get_pll_sys_derive()
301 u32 freq, reg; in mxc_get_pll_enet_derive() local
309 return freq / 2; in mxc_get_pll_enet_derive()
313 return freq / 4; in mxc_get_pll_enet_derive()
345 u32 freq, reg; in mxc_get_pll_ddr_derive() local
352 return freq; in mxc_get_pll_ddr_derive()
477 u32 reg, freq; in get_ddrc_clk() local
914 freq = (freq * (1 << i)); in mxs_set_lcdclk()
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/u-boot/drivers/sound/
A Dsound.c12 uint freq, uint channels) in sound_create_square_wave() argument
15 const int period = freq ? sample_rate / freq : 0; in sound_create_square_wave()
18 assert(freq); in sound_create_square_wave()
A Dmax98090.c82 int max98090_set_sysclk(struct maxim_priv *priv, unsigned int freq) in max98090_set_sysclk() argument
87 if (freq == priv->sysclk) in max98090_set_sysclk()
95 if (freq >= 10000000 && freq < 20000000) { in max98090_set_sysclk()
98 } else if (freq >= 20000000 && freq < 40000000) { in max98090_set_sysclk()
101 } else if (freq >= 40000000 && freq < 60000000) { in max98090_set_sysclk()
109 debug("%s: Clock at %uHz\n", __func__, freq); in max98090_set_sysclk()
114 priv->sysclk = freq; in max98090_set_sysclk()
/u-boot/drivers/ddr/marvell/axp/
A Dddr3_hw_training.c85 u32 freq, reg; in ddr3_hw_training() local
193 freq = DDR_100; in ddr3_hw_training()
196 freq = DDR_300; in ddr3_hw_training()
213 ddr3_print_freq(freq); in ddr3_hw_training()
233 freq, tmp_ratio, in ddr3_hw_training()
253 freq, tmp_ratio, in ddr3_hw_training()
296 freq = DDR_400; in ddr3_hw_training()
308 ddr3_print_freq(freq); in ddr3_hw_training()
382 freq, tmp_ratio, in ddr3_hw_training()
917 u32 freq, reg; in ddr3_training_suspend_resume() local
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/u-boot/arch/arm/include/asm/arch-mxs/
A Dclock.h45 void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
46 void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
47 void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
48 void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq);
/u-boot/arch/arm/mach-imx/mx6/
A Dclock.c284 u64 freq; in mxc_get_pll_pfd() local
312 u32 reg, freq; in get_mcu_main_clk() local
319 return freq / (reg + 1); in get_mcu_main_clk()
340 freq = MXC_HCLK; in get_periph_clk()
369 return freq / (div + 1); in get_periph_clk()
408 freq = MXC_HCLK; in get_uart_clk()
497 freq = MXC_HCLK; in get_mmdc_ch0_clk()
667 freq *= post_div; in mxs_set_lcdclk()
681 temp = freq * i * j; in mxs_set_lcdclk()
915 if (freq < ENET_25MHZ || freq > ENET_125MHZ) in enable_fec_anatop_clock()
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/u-boot/board/friendlyarm/nanopi2/
A Dlcds.c99 .freq = 60,
126 .freq = 61,
153 .freq = 61,
180 .freq = 61,
207 .freq = 61,
234 .freq = 60,
261 .freq = 60,
287 .freq = 61,
314 .freq = 61,
340 .freq = 60,
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/u-boot/board/freescale/t208xrdb/
A Dt208xrdb.c32 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; in checkboard() local
56 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); in checkboard()
57 printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]); in checkboard()
/u-boot/board/phytec/phycore_am335x_r2/
A Dboard.c170 int freq = am335x_get_efuse_mpu_max_freq(cdev); in get_dpll_mpu_params() local
172 switch (freq) { in get_dpll_mpu_params()
190 static void scale_vcores_generic(int freq) in scale_vcores_generic() argument
207 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq); in scale_vcores_generic()
223 int freq; in scale_vcores() local
225 freq = am335x_get_efuse_mpu_max_freq(cdev); in scale_vcores()
226 scale_vcores_generic(freq); in scale_vcores()
/u-boot/drivers/ram/rockchip/
A Ddmc-rk3368.c387 if (freq <= 400000000) in ddrphy_config_delays()
392 if (freq < 681000000) in ddrphy_config_delays()
444 return ps_to_tCK(ns * 1000, freq); in ns_to_tCK()
454 ulong freq) in pctl_calc_timings() argument
476 if (freq <= (400 * MHz)) { in pctl_calc_timings()
479 } else if (freq <= (533 * MHz)) { in pctl_calc_timings()
482 } else if (freq <= (666 * MHz)) { in pctl_calc_timings()
500 pctl_timing->tras = ps_to_tCK(35000, freq); in pctl_calc_timings()
501 pctl_timing->trc = ps_to_tCK(48750, freq); in pctl_calc_timings()
505 pctl_timing->twr = ps_to_tCK(15000, freq); in pctl_calc_timings()
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/u-boot/cmd/
A Dspi.c31 static unsigned int freq; variable
49 ret = spi_get_bus_and_cs(bus, cs, freq, mode, "spi_generic_drv", in do_spi_xfer()
54 slave = spi_setup_slave(bus, cs, freq, mode); in do_spi_xfer()
110 if (freq == 0) in do_spi()
111 freq = 1000000; in do_spi()
127 freq = simple_strtoul(cp+1, &cp, 10); in do_spi()
/u-boot/drivers/video/meson/
A Dmeson_vclk.c628 unsigned int freq, in meson_hdmi_pll_find_params() argument
641 freq, *m, *frac, *od); in meson_hdmi_pll_find_params()
652 unsigned int freq) in meson_vclk_dmt_supported_freq() argument
657 freq *= 10; in meson_vclk_dmt_supported_freq()
930 unsigned int freq; in meson_vclk_setup() local
967 for (freq = 0 ; params[freq].pixel_freq ; ++freq) { in meson_vclk_setup()
979 if (freq == MESON_VCLK_HDMI_DDR_54000 && in meson_vclk_setup()
987 if (freq == MESON_VCLK_HDMI_148500 && in meson_vclk_setup()
994 if (!params[freq].pixel_freq) { in meson_vclk_setup()
1000 params[freq].pll_od1, params[freq].pll_od2, in meson_vclk_setup()
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