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Searched refs:gate_reg (Results 1 – 3 of 3) sorted by relevance

/u-boot/drivers/clk/altera/
A Dclk-arria10.c41 u16 gate_reg; member
92 if (!enable && plat->gate_reg) in socfpga_a10_clk_endisable()
93 clrbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit)); in socfpga_a10_clk_endisable()
106 if (enable && plat->gate_reg) in socfpga_a10_clk_endisable()
107 setbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit)); in socfpga_a10_clk_endisable()
342 plat->gate_reg = gatereg[0]; in socfpga_a10_of_to_plat()
/u-boot/drivers/clk/mediatek/
A Dclk-mtk.h113 u32 gate_reg; member
128 .gate_reg = _reg, \
160 .gate_reg = _mux_ofs, \
A Dclk-mtk.c361 val = readl(priv->base + mux->gate_reg); in mtk_topckgen_enable()
363 writel(val, priv->base + mux->gate_reg); in mtk_topckgen_enable()
394 val = readl(priv->base + mux->gate_reg); in mtk_topckgen_disable()
396 writel(val, priv->base + mux->gate_reg); in mtk_topckgen_disable()

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