Searched refs:gcr (Results 1 – 16 of 16) sorted by relevance
| /u-boot/arch/powerpc/cpu/mpc85xx/ |
| A D | interrupts.c | 39 out_be32(&pic->gcr, MPC85xx_PICGCR_RST); in interrupt_init_cpu()
40 while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) in interrupt_init_cpu()
42 out_be32(&pic->gcr, MPC85xx_PICGCR_M); in interrupt_init_cpu()
43 in_be32(&pic->gcr); in interrupt_init_cpu()
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| /u-boot/arch/powerpc/cpu/mpc86xx/ |
| A D | interrupts.c | 43 pic->gcr = MPC86xx_PICGCR_RST; in interrupt_init_cpu()
44 while (pic->gcr & MPC86xx_PICGCR_RST) in interrupt_init_cpu()
46 pic->gcr = MPC86xx_PICGCR_MODE; in interrupt_init_cpu()
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| /u-boot/board/esd/vme8349/ |
| A D | pci.c | 114 out_be32(&immr->pci_ctrl[0].gcr, 0); in pci_init_board()
116 out_be32(&immr->pci_ctrl[0].gcr, 1); in pci_init_board()
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun50i_h6.c | 350 writel(0x0, &mctl_phy->dx[2].gcr[0]); in mctl_com_init()
351 writel(0x0, &mctl_phy->dx[3].gcr[0]); in mctl_com_init()
441 clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800); in mctl_channel_init()
443 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555); in mctl_channel_init()
445 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010); in mctl_channel_init()
506 writel(0x00000909, &mctl_phy->dx[i].gcr[5]); in mctl_channel_init()
513 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val); in mctl_channel_init()
519 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val); in mctl_channel_init()
528 clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff); in mctl_channel_init()
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| A D | dram_sun9i.c | 694 debug("DX2GCR0 reset: 0x%x\n", readl(&mctl_phy->dx[2].gcr[0])); in mctl_channel_init()
695 writel(0x7C000285, &mctl_phy->dx[2].gcr[0]); in mctl_channel_init()
696 writel(0x7C000285, &mctl_phy->dx[3].gcr[0]); in mctl_channel_init()
709 clrbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff); in mctl_channel_init()
710 clrbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
717 clrsetbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff, in mctl_channel_init()
720 setbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
723 setbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
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| A D | dram_sunxi_dw.c | 510 clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask); in mctl_channel_init()
550 writel(0x0, &mctl_ctl->dx[2].gcr); in mctl_channel_init()
551 writel(0x0, &mctl_ctl->dx[3].gcr); in mctl_channel_init()
553 writel(0x0, &mctl_ctl->dx[1].gcr); in mctl_channel_init()
605 writel(0x0, &mctl_ctl->dx[2].gcr); in mctl_channel_init()
606 writel(0x0, &mctl_ctl->dx[3].gcr); in mctl_channel_init()
611 writel(0x0, &mctl_ctl->dx[1].gcr); in mctl_channel_init()
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| /u-boot/arch/powerpc/cpu/mpc83xx/ |
| A D | pci.c | 145 immr->pci_ctrl[i].gcr = 1; in mpc83xx_pci_init()
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | dram_sunxi_dw.h | 140 u32 gcr; /* 0x44 general configuration register */ member
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| A D | dram_sun9i.h | 146 u32 gcr[4]; /* DATX8 general configuration register */ member
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| A D | dram_sun50i_h6.h | 245 u32 gcr[7]; /* 0x00 */ member
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| /u-boot/arch/arm/include/asm/arch-s32v234/ |
| A D | imx-regs.h | 266 u32 gcr; member
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| /u-boot/arch/arm/include/asm/arch-omap3/ |
| A D | cpu.h | 253 u32 gcr; member
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| /u-boot/drivers/clk/ |
| A D | clk_stm32h7.c | 168 u32 gcr; /* 0xa0 Global Control Register */ member
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| /u-boot/arch/powerpc/include/asm/ |
| A D | immap_83xx.h | 421 u32 gcr; member
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| A D | immap_86xx.h | 541 uint gcr; /* 0x41020 - Global Configuration Register */ member
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| A D | immap_85xx.h | 642 u32 gcr; /* Global Configuration */ member
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