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Searched refs:gpio_regs (Results 1 – 25 of 25) sorted by relevance

/u-boot/board/imgtec/ci20/
A Dci20.c35 writel(0x30f00000, gpio_regs + GPIO_PXINTC(4)); in ci20_mux_mmc()
36 writel(0x30f00000, gpio_regs + GPIO_PXMASKC(4)); in ci20_mux_mmc()
39 writel(0x30f00000, gpio_regs + GPIO_PXPENC(4)); in ci20_mux_mmc()
77 writel(3 << 30, gpio_regs + GPIO_PXINTC(0)); in ci20_mux_jtag()
78 writel(3 << 30, gpio_regs + GPIO_PXMASKC(0)); in ci20_mux_jtag()
102 writel(20, gpio_regs + GPIO_PXPENS(0)); in ci20_mux_nand()
113 writel(0x9, gpio_regs + GPIO_PXINTC(5)); in ci20_mux_uart()
114 writel(0x9, gpio_regs + GPIO_PXMASKC(5)); in ci20_mux_uart()
115 writel(0x9, gpio_regs + GPIO_PXPAT1C(5)); in ci20_mux_uart()
116 writel(0x9, gpio_regs + GPIO_PXPAT0C(5)); in ci20_mux_uart()
[all …]
/u-boot/arch/mips/mach-jz47xx/jz4780/
A Dgpio.c11 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in jz47xx_gpio_get_value() local
15 return readl(gpio_regs + GPIO_PXPIN(port)) & BIT(pin); in jz47xx_gpio_get_value()
20 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in jz47xx_gpio_direction_input() local
24 writel(BIT(pin), gpio_regs + GPIO_PXINTC(port)); in jz47xx_gpio_direction_input()
25 writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port)); in jz47xx_gpio_direction_input()
26 writel(BIT(pin), gpio_regs + GPIO_PXPAT1S(port)); in jz47xx_gpio_direction_input()
31 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in jz47xx_gpio_direction_output() local
35 writel(BIT(pin), gpio_regs + GPIO_PXINTC(port)); in jz47xx_gpio_direction_output()
36 writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port)); in jz47xx_gpio_direction_output()
37 writel(BIT(pin), gpio_regs + GPIO_PXPAT1C(port)); in jz47xx_gpio_direction_output()
[all …]
/u-boot/drivers/gpio/
A Dmxc_gpio.c32 struct gpio_regs *regs;
36 struct gpio_regs *regs;
77 struct gpio_regs *regs; in mxc_gpio_direction()
85 regs = (struct gpio_regs *)gpio_ports[port]; in mxc_gpio_direction()
104 struct gpio_regs *regs; in gpio_set_value()
112 regs = (struct gpio_regs *)gpio_ports[port]; in gpio_set_value()
127 struct gpio_regs *regs; in gpio_get_value()
135 regs = (struct gpio_regs *)gpio_ports[port]; in gpio_get_value()
319 plat->regs = (struct gpio_regs *)addr; in mxc_gpio_of_to_plat()
352 { 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
[all …]
A Dimx_rgpio2p.c25 struct gpio_regs *regs;
30 struct gpio_regs *regs;
33 static int imx_rgpio2p_is_output(struct gpio_regs *regs, int offset) in imx_rgpio2p_is_output()
42 static void imx_rgpio2p_bank_direction(struct gpio_regs *regs, int offset, in imx_rgpio2p_bank_direction()
186 plat->regs = (struct gpio_regs *)addr; in imx_rgpio2p_bind()
211 { 0, (struct gpio_regs *)RGPIO2P_GPIO1_BASE_ADDR },
212 { 1, (struct gpio_regs *)RGPIO2P_GPIO2_BASE_ADDR },
213 { 2, (struct gpio_regs *)RGPIO2P_GPIO3_BASE_ADDR },
214 { 3, (struct gpio_regs *)RGPIO2P_GPIO4_BASE_ADDR },
215 { 4, (struct gpio_regs *)RGPIO2P_GPIO5_BASE_ADDR },
[all …]
A Dspear_gpio.c20 struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE; in gpio_direction()
37 struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE; in gpio_set_value()
49 struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE; in gpio_get_value()
A Dlpc32xx_gpio.c41 struct gpio_regs *regs;
71 struct gpio_regs *regs = gpio_priv->regs; in lpc32xx_gpio_direction_input()
113 struct gpio_regs *regs = gpio_priv->regs; in lpc32xx_gpio_get_value()
153 struct gpio_regs *regs = gpio_priv->regs; in gpio_set()
187 struct gpio_regs *regs = gpio_priv->regs; in gpio_clr()
235 struct gpio_regs *regs = gpio_priv->regs; in lpc32xx_gpio_direction_output()
306 gpio_priv->regs = (struct gpio_regs *)GPIO_BASE; in lpc32xx_gpio_probe()
A Dxilinx_gpio.c19 struct gpio_regs { struct
25 struct gpio_regs *regs; argument
271 plat->regs = (struct gpio_regs *)dev_read_addr(dev); in xilinx_gpio_of_to_plat()
/u-boot/board/tplink/wdr4300/
A Dwdr4300.c21 void __iomem *gpio_regs = map_physmem(AR71XX_GPIO_BASE, in wdr4300_usb_start() local
23 if (!gpio_regs) in wdr4300_usb_start()
27 clrbits_be32(gpio_regs + AR71XX_GPIO_REG_OE, BIT(21) | BIT(22)); in wdr4300_usb_start()
28 writel(BIT(21) | BIT(22), gpio_regs + AR71XX_GPIO_REG_SET); in wdr4300_usb_start()
/u-boot/arch/arm/cpu/arm920t/ep93xx/
A Dled.c17 register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; in switch_LED_on()
25 register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE; in switch_LED_off()
/u-boot/board/netgear/dgnd3700v2/
A Ddgnd3700v2.c20 void __iomem *gpio_regs = map_physmem(GPIO_BASE_6362, 0, MAP_NOCACHE); in board_early_init_f() local
23 setbits_be32(gpio_regs + GPIO_MODE_6362_REG, in board_early_init_f()
/u-boot/board/timll/devkit3250/
A Ddevkit3250_spl.c16 static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
/u-boot/arch/arm/include/asm/arch-mx27/
A Dgpio.h12 struct gpio_regs { struct
35 struct gpio_regs port[6]; argument
/u-boot/board/st/stv0991/
A Dstv0991.c24 struct gpio_regs *const gpioa_regs =
25 (struct gpio_regs *) GPIOA_BASE_ADDR;
/u-boot/arch/arm/include/asm/arch-imxrt/
A Dgpio.h12 struct gpio_regs { struct
/u-boot/arch/arm/include/asm/arch-stv0991/
A Dgpio.h15 struct gpio_regs { struct
/u-boot/arch/arm/include/asm/arch-spear/
A Dgpio.h15 struct gpio_regs { struct
/u-boot/arch/arm/include/asm/arch-imx8/
A Dgpio.h11 struct gpio_regs { struct
/u-boot/arch/arm/include/asm/mach-imx/
A Dgpio.h13 struct gpio_regs { struct
/u-boot/arch/arm/include/asm/arch-mx7ulp/
A Dgpio.h9 struct gpio_regs { struct
/u-boot/arch/sh/include/asm/
A Dcpu_sh7752.h100 struct gpio_regs { struct
193 #define GPIO_BASE ((struct gpio_regs *)0xffec0000) argument
A Dcpu_sh7753.h100 struct gpio_regs { struct
193 #define GPIO_BASE ((struct gpio_regs *)0xffec0000) argument
/u-boot/arch/arm/include/asm/arch-lpc32xx/
A Dgpio.h13 struct gpio_regs { struct
/u-boot/board/BuR/brppt2/
A Dboard.c406 struct gpio_regs *gpio = (struct gpio_regs *)GPIO2_BASE_ADDR; in spl_dram_init()
/u-boot/arch/arm/include/asm/arch-ep93xx/
A Dep93xx.h478 struct gpio_regs { struct
/u-boot/board/boundary/nitrogen6x/
A Dnitrogen6x.c879 struct gpio_regs *regs = (struct gpio_regs *)GPIO6_BASE_ADDR; in checkboard()

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