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Searched refs:grp (Results 1 – 25 of 38) sorted by relevance

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/u-boot/drivers/pinctrl/uniphier/
A Dpinctrl-uniphier.h117 #define __UNIPHIER_PINCTRL_GROUP(grp) \ argument
119 .name = #grp, \
120 .pins = grp##_pins, \
121 .num_pins = ARRAY_SIZE(grp##_pins), \
122 .muxvals = grp##_muxvals + \
123 BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \
124 ARRAY_SIZE(grp##_muxvals)), \
134 #define UNIPHIER_PINCTRL_GROUP(grp) \ argument
135 { .num_pins = ARRAY_SIZE(grp##_pins) + ARRAY_SIZE(grp##_muxvals) }
138 #define UNIPHIER_PINCTRL_GROUP(grp) __UNIPHIER_PINCTRL_GROUP(grp) argument
[all …]
A Dpinctrl-uniphier-core.c320 const struct uniphier_pinctrl_group *grp = in uniphier_pinconf_group_set() local
324 for (i = 0; i < grp->num_pins; i++) { in uniphier_pinconf_group_set()
325 ret = uniphier_pinconf_set(dev, grp->pins[i], param, arg); in uniphier_pinconf_group_set()
392 const struct uniphier_pinctrl_group *grp = in uniphier_pinmux_group_set() local
396 for (i = 0; i < grp->num_pins; i++) in uniphier_pinmux_group_set()
397 uniphier_pinmux_set_one(dev, grp->pins[i], grp->muxvals[i]); in uniphier_pinmux_group_set()
/u-boot/arch/arm/mach-tegra/
A Dpinmux-common.c85 #define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4)) argument
86 #define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2) argument
88 #define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4)) argument
89 #define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2) argument
91 #define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4)) argument
92 #define TRI_SHIFT(grp) ((grp) % 32) argument
383 u32 *reg = REG(grp); in pinmux_set_schmt()
408 u32 *reg = REG(grp); in pinmux_set_hsm()
518 u32 *reg = DRV_REG(grp); in pinmux_set_drvup_slwf()
539 u32 *reg = DRV_REG(grp); in pinmux_set_drvdn_slwr()
[all …]
/u-boot/arch/arm/mach-mvebu/serdes/axp/
A Dboard_env_spec.h100 #define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00) argument
102 #define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04) argument
103 #define GPP_BLINK_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x08) argument
104 #define GPP_DATA_IN_POL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x0C) argument
105 #define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10) argument
106 #define GPP_INT_CAUSE_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x14) argument
107 #define GPP_INT_MASK_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x18) argument
108 #define GPP_INT_LVL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x1C) argument
109 #define GPP_OUT_SET_REG(grp) (0x18130 + ((grp) * 0x40)) argument
111 #define GPP_OUT_CLEAR_REG(grp) (0x18134 + ((grp) * 0x40)) argument
/u-boot/arch/x86/cpu/tangier/
A Dacpi.c72 static u32 acpi_fill_csrt_dma(struct acpi_csrt_group *grp) in acpi_fill_csrt_dma() argument
74 struct acpi_csrt_shared_info *si = (struct acpi_csrt_shared_info *)&grp[1]; in acpi_fill_csrt_dma()
77 memset(grp, 0, sizeof(*grp)); in acpi_fill_csrt_dma()
78 grp->shared_info_length = sizeof(struct acpi_csrt_shared_info); in acpi_fill_csrt_dma()
79 grp->length = sizeof(struct acpi_csrt_group) + grp->shared_info_length; in acpi_fill_csrt_dma()
81 sprintf((char *)&grp->vendor_id, "%04X", 0x8086); in acpi_fill_csrt_dma()
82 grp->device_id = 0x11a2; in acpi_fill_csrt_dma()
100 return grp->length; in acpi_fill_csrt_dma()
/u-boot/arch/arm/dts/
A Dimx6ull-colibri.dtsi245 pinctrl_enet2: enet2-grp {
287 pinctrl_gpio1: gpio1-grp {
319 pinctrl_gpio4: gpio4-grp {
362 pinctrl_i2c1: i2c1-grp {
376 pinctrl_i2c2: i2c2-grp {
422 pinctrl_pwm4: pwm4-grp {
428 pinctrl_pwm5: pwm5-grp {
434 pinctrl_pwm6: pwm6-grp {
440 pinctrl_pwm7: pwm7-grp {
446 pinctrl_uart1: uart1-grp {
[all …]
A Dimx6qdl-dhcom.dtsi231 pinctrl_ecspi1: ecspi1-grp {
241 pinctrl_ecspi2: ecspi2-grp {
282 pinctrl_i2c1: i2c1-grp {
289 pinctrl_i2c2: i2c2-grp {
296 pinctrl_i2c3: i2c3-grp {
321 pinctrl_uart1: uart1-grp {
334 pinctrl_uart4: uart4-grp {
341 pinctrl_uart5: uart5-grp {
350 pinctrl_usbh1: usbh1-grp {
356 pinctrl_usbotg: usbotg-grp {
[all …]
A Dimx7-colibri.dtsi134 pinctrl_i2c4: i2c4-grp {
141 pinctrl_i2c4_gpio: i2c4-gpio-grp {
148 pinctrl_uart1: uart1-grp {
157 pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
164 pinctrl_usdhc1: usdhc1-grp {
175 pinctrl_lcdif_dat: lcdif-dat-grp {
198 pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
242 pinctrl_i2c1: i2c1-grp {
249 pinctrl_i2c1_gpio: i2c1-gpio-grp {
256 pinctrl_cd_usdhc1: usdhc1-cd-grp {
A Dimx6qdl-dhcom-pdk2.dtsi61 pinctrl_hog: hog-grp {
90 pinctrl_audmux_ext: audmux-ext-grp {
99 pinctrl_enet_1G: enet-1G-grp {
122 pinctrl_pcie: pcie-grp {
A Dimx6qdl-sabrelite.dtsi64 pinctrl_i2c1_1: i2c1-1grp {
80 pinctrl_i2c2_1: i2c2-1grp {
99 pinctrl_i2c3_1: i2c3-1grp {
A Dimx6ull-dart-6ul.dts82 pinctrl_enet2_rst: enet2-rst-grp {
/u-boot/drivers/pinctrl/mtmips/
A Dpinctrl-mtmips-common.c45 const struct mtmips_pmx_group *grp = &priv->groups[group_selector]; in mtmips_pinmux_group_set() local
49 if (!grp->nfuncs) in mtmips_pinmux_group_set()
52 for (i = 0; i < grp->nfuncs; i++) { in mtmips_pinmux_group_set()
53 if (!strcmp(grp->funcs[i].name, func->name)) { in mtmips_pinmux_group_set()
54 mtmips_pinctrl_reg_set(priv, grp->reg, grp->shift, in mtmips_pinmux_group_set()
55 grp->mask, grp->funcs[i].value); in mtmips_pinmux_group_set()
/u-boot/drivers/ddr/marvell/a38x/
A Dmv_ddr_sys_env_lib.h18 #define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00) argument
19 #define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04) argument
20 #define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10) argument
/u-boot/drivers/pinctrl/meson/
A Dpinctrl-meson-gx.h25 #define GROUP(grp, r, b) \ argument
27 .name = #grp, \
28 .pins = grp ## _pins, \
29 .num_pins = ARRAY_SIZE(grp ## _pins), \
A Dpinctrl-meson-axg.h43 #define GROUP(grp, f) \ argument
45 .name = #grp, \
46 .pins = grp ## _pins, \
47 .num_pins = ARRAY_SIZE(grp ## _pins), \
/u-boot/drivers/pinctrl/mvebu/
A Dpinctrl-armada-37xx.c231 if (!strcmp(grp->funcs[f], func)) in armada_37xx_get_func_reg()
278 unsigned int mask = grp->reg_mask; in armada_37xx_pmx_set_by_name()
282 name, grp->name); in armada_37xx_pmx_set_by_name()
289 val = grp->val[func]; in armada_37xx_pmx_set_by_name()
360 grp->pins = devm_kzalloc(info->dev, in armada_37xx_fill_group()
361 (grp->npins + grp->extra_npins) * in armada_37xx_fill_group()
363 if (!grp->pins) in armada_37xx_fill_group()
366 for (i = 0; i < grp->npins; i++) in armada_37xx_fill_group()
367 grp->pins[i] = grp->start_pin + i; in armada_37xx_fill_group()
370 grp->pins[i+j] = grp->extra_pin + j; in armada_37xx_fill_group()
[all …]
/u-boot/arch/arm/mach-imx/mx6/
A Dddr.c767 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; in mx6sl_dram_iocfg()
768 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; in mx6sl_dram_iocfg()
770 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; in mx6sl_dram_iocfg()
771 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; in mx6sl_dram_iocfg()
834 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; in mx6dq_dram_iocfg()
835 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; in mx6dq_dram_iocfg()
837 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; in mx6dq_dram_iocfg()
838 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; in mx6dq_dram_iocfg()
841 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds; in mx6dq_dram_iocfg()
912 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; in mx6sdl_dram_iocfg()
[all …]
/u-boot/arch/arm/mach-tegra/tegra20/
A Dfuncmux.c16 #define PINMUX(grp, mux, pupd, tri) \ argument
17 {PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
211 enum pmux_pingrp grp[] = {PMUX_PINGRP_KBCA, in funcmux_select() enum
217 for (i = 0; i < ARRAY_SIZE(grp); i++) { in funcmux_select()
218 pinmux_tristate_disable(grp[i]); in funcmux_select()
219 pinmux_set_func(grp[i], PMUX_FUNC_KBC); in funcmux_select()
220 pinmux_set_pullupdown(grp[i], PMUX_PULL_UP); in funcmux_select()
/u-boot/arch/arm/mach-mvebu/serdes/a38x/
A Dsys_env_lib.h241 #define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00) argument
242 #define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04) argument
243 #define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10) argument
/u-boot/drivers/ddr/altera/
A Dsequencer.c401 scc_mgr_set(off, grp, val); in scc_mgr_set_all_ranks()
1644 rw_mgr_incr_vfifo(grp); in rw_mgr_decr_vfifo()
1654 const u32 grp) in find_vfifo_failing_read() argument
1671 rw_mgr_incr_vfifo(grp); in find_vfifo_failing_read()
1745 rw_mgr_incr_vfifo(grp); in sdr_find_phase()
1805 rw_mgr_decr_vfifo(seq, grp); in sdr_backup_phase()
1830 rw_mgr_incr_vfifo(grp); in sdr_backup_phase()
1855 rw_mgr_incr_vfifo(grp); in sdr_nonworking_phase()
1933 rw_mgr_incr_vfifo(grp); in sdr_find_window_center()
1950 const u32 grp) in rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() argument
[all …]
/u-boot/board/friendlyarm/nanopi2/
A Dboard.c42 int grp; member
50 [0] = { .grp = gpio_d, .bit = 1, .io_fn = 0 }, in bd_pwm_config_gpio()
51 [1] = { .grp = gpio_c, .bit = 13, .io_fn = 1 }, in bd_pwm_config_gpio()
52 [2] = { .grp = gpio_c, .bit = 14, .io_fn = 1 }, in bd_pwm_config_gpio()
53 [3] = { .grp = gpio_d, .bit = 0, .io_fn = 0 }, in bd_pwm_config_gpio()
56 int gp = pwm_dev[ch].grp; in bd_pwm_config_gpio()
/u-boot/drivers/net/mscc_eswitch/
A Dmscc_xfer.c64 u8 grp = 0; /* Recv everything on CPU group 0 */ in mscc_recv() local
69 BIT(grp))) in mscc_recv()
/u-boot/drivers/net/phy/
A Dmicrel_ksz90x1.c82 const struct ksz90x1_reg_field *grp; member
136 val[i] = ofnode_read_u32_default(node, ofcfg->grp[i].name, ~0); in ksz90x1_of_config_group()
137 offset = ofcfg->grp[i].off; in ksz90x1_of_config_group()
140 regval |= ofcfg->grp[i].dflt << offset; in ksz90x1_of_config_group()
144 max = (1 << ofcfg->grp[i].size) - 1; in ksz90x1_of_config_group()
/u-boot/drivers/pinctrl/mediatek/
A Dpinctrl-mtk-common.c269 const struct mtk_group_desc *grp = in mtk_pinmux_group_set() local
273 for (i = 0; i < grp->num_pins; i++) { in mtk_pinmux_group_set()
274 int *pin_modes = grp->data; in mtk_pinmux_group_set()
276 mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE, in mtk_pinmux_group_set()
498 const struct mtk_group_desc *grp = in mtk_pinconf_group_set() local
502 for (i = 0; i < grp->num_pins; i++) { in mtk_pinconf_group_set()
503 ret = mtk_pinconf_set(dev, grp->pins[i], param, arg); in mtk_pinconf_group_set()
/u-boot/drivers/pinctrl/renesas/
A Dpfc.c600 const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector]; in sh_pfc_pinctrl_group_set() local
607 for (i = 0; i < grp->nr_pins; ++i) { in sh_pfc_pinctrl_group_set()
608 idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); in sh_pfc_pinctrl_group_set()
612 if (!strcmp(cfg->name, grp->name)) in sh_pfc_pinctrl_group_set()
627 for (i = 0; i < grp->nr_pins; ++i) { in sh_pfc_pinctrl_group_set()
628 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); in sh_pfc_pinctrl_group_set()
632 idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); in sh_pfc_pinctrl_group_set()
827 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector]; in sh_pfc_pinconf_group_set() local
830 for (i = 0; i < grp->nr_pins; i++) in sh_pfc_pinconf_group_set()
831 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg); in sh_pfc_pinconf_group_set()

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