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Searched refs:hart (Results 1 – 12 of 12) sorted by relevance

/u-boot/arch/riscv/lib/
A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi() argument
39 en = ENABLE_HART_IPI >> hart; in enable_ipi()
40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
106 int riscv_get_ipi(int hart, int *pending) in riscv_get_ipi() argument
[all …]
A Dsifive_clint.c19 #define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4) argument
40 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
42 writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); in riscv_send_ipi()
47 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
49 writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); in riscv_clear_ipi()
54 int riscv_get_ipi(int hart, int *pending) in riscv_get_ipi() argument
56 *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart)); in riscv_get_ipi()
A Dsmp.c85 void handle_ipi(ulong hart) in handle_ipi() argument
88 void (*smp_function)(ulong hart, ulong arg0, ulong arg1); in handle_ipi()
90 if (hart >= CONFIG_NR_CPUS) in handle_ipi()
98 if (!__smp_load_acquire(&gd->arch.ipi[hart].valid)) in handle_ipi()
101 smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr; in handle_ipi()
108 ret = riscv_clear_ipi(hart); in handle_ipi()
110 pr_err("Cannot clear IPI of hart %ld (error %d)\n", hart, ret); in handle_ipi()
114 smp_function(hart, gd->arch.ipi[hart].arg0, gd->arch.ipi[hart].arg1); in handle_ipi()
A Dsbi_ipi.c16 int riscv_send_ipi(int hart) in riscv_send_ipi() argument
20 mask = 1UL << hart; in riscv_send_ipi()
26 int riscv_clear_ipi(int hart) in riscv_clear_ipi() argument
33 int riscv_get_ipi(int hart, int *pending) in riscv_get_ipi() argument
A Dspl.c41 typedef void __noreturn (*image_entry_riscv_t)(ulong hart, void *dtb); in jump_to_image_no_args()
A Dbootm.c83 void (*kernel)(ulong hart, void *dtb); in boot_jump_linux()
/u-boot/drivers/cache/
A Dcache-v5l2.c56 #define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10) argument
60 #define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4)) argument
61 #define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4)) argument
62 #define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4)) argument
63 #define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4)) argument
90 u8 hart = gd->arch.boot_hart; in v5l2_disable() local
91 void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart); in v5l2_disable()
96 while ((readl(&regs->cctl_status) & CCTL_STATUS_MSK(hart))) { in v5l2_disable()
97 if ((readl(&regs->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) { in v5l2_disable()
/u-boot/arch/riscv/include/asm/
A Dsmp.h46 void handle_ipi(ulong hart);
80 int riscv_send_ipi(int hart);
90 int riscv_clear_ipi(int hart);
102 int riscv_get_ipi(int hart, int *pending);
/u-boot/arch/riscv/cpu/
A Dcpu.c81 static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1) in dummy_pending_ipi_clear() argument
/u-boot/doc/board/microchip/
A Dmpfs_icicle.rst60 (Note: HSS git repo is at https://github.com/polarfire-soc/hart-software-services)
96 cd hart-software-services/tools/hss-payload-generator
98 3. Edit test/uboot.yaml file for hart entry points and correct name of the binary file.
100 …hart-entry-points: {u54_1: '0x80200000', u54_2: '0x80200000', u54_3: '0x80200000', u54_4: '0x80200…
103 …tb.bin: {exec-addr: '0x80200000', owner-hart: u54_1, secondary-hart: u54_2, secondary-hart: u54_3,…
114 (Note: HSS git repo is at https://github.com/polarfire-soc/hart-software-services/blob/master/tools…
144 (Note: HSS git repo is at https://github.com/polarfire-soc/hart-software-services)
173 cd hart-software-services/tools/hss-payload-generator
175 3. Edit test/uboot.yaml file for hart entry points and correct name of the binary file.
177 …hart-entry-points: {u54_1: '0x80000000', u54_2: '0x80000000', u54_3: '0x80000000', u54_4: '0x80000…
[all …]
/u-boot/doc/board/sipeed/
A Dmaix.rst330 Note that this will only start a program on one hart. As-of this writing it is
572 4. One hart is chosen as a boot hart.
587 7. The boot hart sends an IPI to the other hart telling it to jump to the next
589 8. The boot hart jumps to ``0x80000000``.
/u-boot/arch/riscv/
A DKconfig233 hart need to boot and enter operating system. The booting hart can

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