| /u-boot/drivers/ddr/marvell/axp/ |
| A D | ddr3_init.c | 1141 u32 tmp, hclk; in get_target_freq() local
1145 hclk = 84; in get_target_freq()
1158 hclk = 150; in get_target_freq()
1164 hclk = 165; in get_target_freq()
1168 hclk = 180; in get_target_freq()
1175 hclk = 200; in get_target_freq()
1180 hclk = 222; in get_target_freq()
1186 hclk = 250; in get_target_freq()
1192 hclk = 267; in get_target_freq()
1198 hclk = 300; in get_target_freq()
[all …]
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| A D | ddr3_dfs.c | 127 u32 hclk; in ddr3_dfs_high_2_low() local
129 get_target_freq(cpu_freq, &tmp, &hclk); in ddr3_dfs_high_2_low()
783 u32 hclk; in ddr3_dfs_low_2_high() local
785 get_target_freq(cpu_freq, &tmp, &hclk); in ddr3_dfs_low_2_high()
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| /u-boot/arch/arm/dts/ |
| A D | stm32mp153.dtsi | 34 clock-names = "hclk", "cclk";
47 clock-names = "hclk", "cclk";
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| A D | zynqmp-clk-ccf.dtsi | 179 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
186 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
193 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
200 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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| A D | at91sam9x5_macb1.dtsi | 50 clock-names = "hclk", "pclk";
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| A D | sama7g5.dtsi | 154 clock-names = "hclk", "pclk", "tx_clk";
165 clock-names = "pclk", "hclk";
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| A D | sama5d3_emac.dtsi | 50 clock-names = "hclk", "pclk";
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| A D | at91sam9x5_macb0.dtsi | 62 clock-names = "hclk", "pclk";
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| A D | at91sam9261.dtsi | 78 clock-names = "ohci_clk", "hclk", "uhpck";
89 clock-names = "lcdc_clk", "hclk";
131 clock-names = "pclk", "hclk";
714 hclk0: hclk@16 {
720 hclk1: hclk@17 {
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| A D | mt8518.dtsi | 97 clock-names = "source", "hclk", "source_cg";
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| A D | mt8516.dtsi | 122 clock-names = "source", "hclk", "source_cg";
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| A D | mt8512.dtsi | 158 clock-names = "source", "hclk", "source_cg";
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| A D | sama5d3_gmac.dtsi | 83 clock-names = "hclk", "pclk";
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| A D | mt7622.dtsi | 186 clock-names = "source", "hclk";
196 clock-names = "source", "hclk";
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| A D | mt7623.dtsi | 232 clock-names = "source", "hclk";
242 clock-names = "source", "hclk";
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| A D | at91sam9263.dtsi | 874 clock-names = "hclk", "pclk";
883 clock-names = "pclk", "hclk";
1008 clock-names = "lcdc_clk", "hclk";
1035 clock-names = "ohci_clk", "hclk", "uhpck";
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| A D | sam9x60.dtsi | 104 clock-names = "hclk", "pclk";
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| A D | zynq-7000.dtsi | 282 clock-names = "pclk", "hclk", "tx_clk";
293 clock-names = "pclk", "hclk", "tx_clk";
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| A D | zynqmp.dtsi | 524 clock-names = "pclk", "hclk", "tx_clk";
538 clock-names = "pclk", "hclk", "tx_clk";
552 clock-names = "pclk", "hclk", "tx_clk";
566 clock-names = "pclk", "hclk", "tx_clk";
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| /u-boot/arch/arm/mach-s5pc1xx/ |
| A D | clock.c | 217 unsigned long hclk; in get_hclk_sys() local
236 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1); in get_hclk_sys()
238 return hclk; in get_hclk_sys()
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| /u-boot/drivers/mtd/nand/raw/ |
| A D | lpc32xx_nand_slc.c | 114 uint32_t hclk = get_hclk_clk_rate(); in lpc32xx_nand_init() local
129 TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) | in lpc32xx_nand_init()
130 TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) | in lpc32xx_nand_init()
131 TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | in lpc32xx_nand_init()
133 TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) | in lpc32xx_nand_init()
134 TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) | in lpc32xx_nand_init()
135 TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP), in lpc32xx_nand_init()
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| /u-boot/board/menlo/m53menlo/ |
| A D | m53menlo.c | 171 static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk) in enable_lvds_clock() argument
183 ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK); in enable_lvds_clock()
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| /u-boot/doc/device-tree-bindings/clock/ |
| A D | nvidia,tegra20-car.txt | 140 109 hclk
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| /u-boot/arch/riscv/dts/ |
| A D | microchip-mpfs-icicle-kit.dts | 377 clock-names = "pclk", "hclk";
396 clock-names = "pclk", "hclk";
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| /u-boot/arch/mips/dts/ |
| A D | mt7620.dtsi | 290 clock-names = "source", "hclk";
|