Searched refs:i2c_base (Results 1 – 9 of 9) sorted by relevance
| /u-boot/drivers/i2c/ |
| A D | davinci_i2c.c | 36 REG(&(i2c_base->i2c_con)) = 0;\
83 REG(&(i2c_base->i2c_drr)); in _flush_rx()
99 REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll)); in _davinci_i2c_setspeed()
115 REG(&(i2c_base->i2c_cnt)) = 0; in _davinci_i2c_init()
138 if (_wait_for_bus(i2c_base)) in _davinci_i2c_read()
217 _flush_rx(i2c_base); in _davinci_i2c_read()
240 if (_wait_for_bus(i2c_base)) in _davinci_i2c_write()
299 _flush_rx(i2c_base); in _davinci_i2c_write()
315 if (_wait_for_bus(i2c_base)) in _davinci_i2c_probe_chip()
327 _flush_rx(i2c_base); in _davinci_i2c_probe_chip()
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| A D | omap24xx_i2c.c | 296 omap_i2c_write_reg(i2c_base, ip_rev, in flush_fifo()
397 omap_i2c_write_reg(i2c_base, ip_rev, in omap24_i2c_deblock()
402 omap_i2c_write_reg(i2c_base, ip_rev, in omap24_i2c_deblock()
466 flush_fifo(i2c_base, ip_rev); in __omap24_i2c_init()
533 flush_fifo(i2c_base, ip_rev); in __omap24_i2c_probe()
688 omap_i2c_write_reg(i2c_base, ip_rev, in __omap24_i2c_read()
692 omap_i2c_write_reg(i2c_base, ip_rev, in __omap24_i2c_read()
699 flush_fifo(i2c_base, ip_rev); in __omap24_i2c_read()
788 omap_i2c_write_reg(i2c_base, ip_rev, in __omap24_i2c_write()
791 omap_i2c_write_reg(i2c_base, ip_rev, in __omap24_i2c_write()
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| A D | designware_i2c.c | 32 writel(ena, &i2c_base->ic_enable); in dw_i2c_enable()
43 writel(ena, &i2c_base->ic_enable); in dw_i2c_enable()
303 dw_i2c_enable(i2c_base, false); in _dw_i2c_set_bus_speed()
335 dw_i2c_enable(i2c_base, true); in _dw_i2c_set_bus_speed()
375 dw_i2c_enable(i2c_base, false); in i2c_setaddress()
380 dw_i2c_enable(i2c_base, true); in i2c_setaddress()
391 readl(&i2c_base->ic_cmd_data); in i2c_flush_rxfifo()
417 if (i2c_wait_for_bb(i2c_base)) in i2c_xfer_init()
420 i2c_setaddress(i2c_base, chip); in i2c_xfer_init()
448 i2c_flush_rxfifo(i2c_base); in i2c_xfer_finish()
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| A D | fsl_i2c.c | 44 static const struct fsl_i2c_base *i2c_base[4] = { variable
503 __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd, in fsl_i2c_init()
509 return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip); in fsl_i2c_probe_chip()
517 return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], in fsl_i2c_read()
526 return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], in fsl_i2c_write()
532 return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed, in fsl_i2c_set_bus_speed()
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| /u-boot/doc/device-tree-bindings/i2c/ |
| A D | nx_i2c.txt | 10 - reg = <i2c_base 0x100>;
11 Where i2c_base has to be the base address of the i2c-register set.
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| /u-boot/board/samsung/arndale/ |
| A D | arndale_spl.c | 36 .i2c_base = 0x12c60000,
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| /u-boot/board/samsung/smdk5250/ |
| A D | smdk5250_spl.c | 38 .i2c_base = 0x12c60000,
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| /u-boot/board/samsung/smdk5420/ |
| A D | smdk5420_spl.c | 38 .i2c_base = 0x12c60000,
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| /u-boot/arch/arm/mach-exynos/include/mach/ |
| A D | spl.h | 55 u32 i2c_base; /* i2c base address */ member
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