Searched refs:ibase (Results 1 – 13 of 13) sorted by relevance
| /u-boot/drivers/usb/mtu3/ |
| A D | mtu3_host.c | 31 void __iomem *ibase = u3h->ippc_base; in ssusb_host_enable() local
40 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN); in ssusb_host_enable()
50 value = mtu3_readl(ibase, SSUSB_U3_CTRL(i)); in ssusb_host_enable()
53 mtu3_writel(ibase, SSUSB_U3_CTRL(i), value); in ssusb_host_enable()
58 value = mtu3_readl(ibase, SSUSB_U2_CTRL(i)); in ssusb_host_enable()
61 mtu3_writel(ibase, SSUSB_U2_CTRL(i), value); in ssusb_host_enable()
73 void __iomem *ibase = u3h->ippc_base; in ssusb_host_disable() local
84 value = mtu3_readl(ibase, SSUSB_U3_CTRL(i)); in ssusb_host_disable()
86 mtu3_writel(ibase, SSUSB_U3_CTRL(i), value); in ssusb_host_disable()
91 value = mtu3_readl(ibase, SSUSB_U2_CTRL(i)); in ssusb_host_disable()
[all …]
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| A D | mtu3_core.c | 85 void __iomem *ibase = mtu->ippc_base; in mtu3_device_enable() local
88 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); in mtu3_device_enable()
92 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0), in mtu3_device_enable()
96 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), in mtu3_device_enable()
105 void __iomem *ibase = mtu->ippc_base; in mtu3_device_disable() local
108 mtu3_setbits(ibase, SSUSB_U3_CTRL(0), in mtu3_device_disable()
111 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), in mtu3_device_disable()
114 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); in mtu3_device_disable()
120 void __iomem *ibase = mtu->ippc_base; in mtu3_device_reset() local
122 mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST); in mtu3_device_reset()
[all …]
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| A D | mtu3_plat.c | 41 void __iomem *ibase = ssusb->ippc_base; in ssusb_check_clocks() local
48 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value, in ssusb_check_clocks()
55 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value, in ssusb_check_clocks()
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| /u-boot/arch/x86/cpu/ |
| A D | irq.c | 89 pirq = readb((uintptr_t)priv->ibase + in pirq_check_irq_routed()
120 writeb(irq, (uintptr_t)priv->ibase + in pirq_assign_irq()
242 dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase); in create_pirq_routing_table()
243 priv->ibase &= ~0xf; in create_pirq_routing_table()
333 writel(0, (uintptr_t)priv->ibase + priv->actl_addr); in irq_enable_sci()
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| /u-boot/arch/x86/include/asm/ |
| A D | irq.h | 54 u32 ibase; member
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| /u-boot/doc/device-tree-bindings/misc/ |
| A D | intel,irq-router.txt | 14 "ibase": IRQ routing is in the memory-mapped IBASE register block
15 - intel,ibase-offset : IBASE register offset in the interrupt router's PCI
16 configuration space, required only if intel,pirq-config = "ibase".
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| /u-boot/arch/x86/dts/ |
| A D | cherryhill.dts | 84 intel,pirq-config = "ibase";
85 intel,ibase-offset = <0x50>;
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| A D | bayleybay.dts | 108 intel,pirq-config = "ibase";
109 intel,ibase-offset = <0x50>;
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| A D | baytrail_som-db5800-som-6867.dts | 132 intel,pirq-config = "ibase";
133 intel,ibase-offset = <0x50>;
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| A D | conga-qeval20-qa3-e3845.dts | 119 intel,pirq-config = "ibase";
120 intel,ibase-offset = <0x50>;
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| A D | dfi-bt700.dtsi | 130 intel,pirq-config = "ibase";
131 intel,ibase-offset = <0x50>;
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| A D | minnowmax.dts | 132 intel,pirq-config = "ibase";
133 intel,ibase-offset = <0x50>;
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| /u-boot/ |
| A D | Makefile | 1209 …/_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print "ibase=16; " toupper(end)…
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