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Searched refs:im (Results 1 – 25 of 33) sorted by relevance

12

/u-boot/board/freescale/mpc8315erdb/
A Dsdram.c52 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; in fixed_sdram()
60 im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; in fixed_sdram()
64 im->ddr.cs_config[1] = 0; in fixed_sdram()
67 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
72 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) in fixed_sdram()
75 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
78 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
79 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; in fixed_sdram()
85 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; in fixed_sdram()
102 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) in dram_init()
[all …]
/u-boot/board/freescale/mpc8313erdb/
A Dsdram.c55 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; in fixed_sdram()
66 im->ddr.csbnds[0].csbnds = in fixed_sdram()
73 im->ddr.cs_config[1] = 0; in fixed_sdram()
82 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) in fixed_sdram()
86 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG; in fixed_sdram()
88 im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2; in fixed_sdram()
89 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
96 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; in fixed_sdram()
105 volatile fsl_lbc_t *lbc = &im->im_lbc; in dram_init()
108 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) in dram_init()
[all …]
/u-boot/board/gdsys/mpc8308/
A Dsdram.c36 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
40 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
43 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); in fixed_sdram()
45 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
49 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
57 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
59 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); in fixed_sdram()
60 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); in fixed_sdram()
66 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); in fixed_sdram()
74 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in dram_init() local
[all …]
/u-boot/board/mpc8308_p1m/
A Dsdram.c29 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
33 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
36 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); in fixed_sdram()
38 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
42 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
50 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
52 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); in fixed_sdram()
53 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); in fixed_sdram()
59 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); in fixed_sdram()
67 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in dram_init() local
[all …]
/u-boot/board/freescale/mpc8308rdb/
A Dsdram.c33 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
37 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
40 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); in fixed_sdram()
42 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
46 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
54 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
56 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); in fixed_sdram()
57 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); in fixed_sdram()
63 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); in fixed_sdram()
71 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in dram_init() local
[all …]
/u-boot/board/freescale/mpc832xemds/
A Dmpc832xemds.c101 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) in dram_init()
132 im->sysconf.ddrlaw[0].ar = in fixed_sdram()
140 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
141 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
142 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
143 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
144 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
145 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; in fixed_sdram()
146 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
147 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; in fixed_sdram()
[all …]
/u-boot/board/freescale/mpc8349emds/
A Dmpc8349emds.c60 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) in dram_init()
112 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
114 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
115 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; in fixed_sdram()
123 im->ddr.csbnds[2].csbnds = in fixed_sdram()
130 im->ddr.cs_config[0] = 0; in fixed_sdram()
131 im->ddr.cs_config[1] = 0; in fixed_sdram()
132 im->ddr.cs_config[3] = 0; in fixed_sdram()
137 im->ddr.sdram_cfg = in fixed_sdram()
147 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
[all …]
/u-boot/drivers/gpio/
A Dmpc83xx_gpio.c54 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in gpio_direction_input() local
66 clrbits_be32(&im->gpio[ctrlr].dir, line_mask); in gpio_direction_input()
74 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in gpio_direction_output() local
94 setbits_be32(&im->gpio[ctrlr].dir, line_mask); in gpio_direction_output()
102 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in gpio_get_value() local
121 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in gpio_set_value() local
152 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in mpc83xx_gpio_init_f() local
159 out_be32(&im->gpio[0].imr, 0); in mpc83xx_gpio_init_f()
160 out_be32(&im->gpio[0].icr, 0); in mpc83xx_gpio_init_f()
168 out_be32(&im->gpio[1].imr, 0); in mpc83xx_gpio_init_f()
[all …]
/u-boot/arch/powerpc/cpu/mpc83xx/
A Dspl_minimal.c25 void cpu_init_f (volatile immap_t * im) in cpu_init_f() argument
36 im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | in cpu_init_f()
42 im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | in cpu_init_f()
48 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | in cpu_init_f()
53 im->sysconf.spcr |= SPCR_TBEN; in cpu_init_f()
57 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; in cpu_init_f()
61 im->sysconf.obir = CONFIG_SYS_OBIR; in cpu_init_f()
79 im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM; in cpu_init_f()
80 im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM; in cpu_init_f()
102 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in get_bus_freq() local
[all …]
A Dcpu_init.c61 void cpu_init_f (volatile immap_t * im) in cpu_init_f() argument
154 __raw_writel(~(RSR_RES), &im->reset.rsr); in cpu_init_f()
170 __raw_readl(&im->im_lbc.lcrr); in cpu_init_f()
174 setbits_be32(&im->sysconf.spcr, SPCR_TBEN); in cpu_init_f()
181 &im->sysconf.sicrh); in cpu_init_f()
190 __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1); in cpu_init_f()
196 __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir); in cpu_init_f()
246 im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT; in cpu_init_f()
247 im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR; in cpu_init_f()
250 im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT; in cpu_init_f()
[all …]
A Dspeed.c81 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in get_clocks() local
137 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) in get_clocks()
140 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); in get_clocks()
142 if (im->reset.rcwh & HRCWH_PCI_HOST) { in get_clocks()
156 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; in get_clocks()
159 sccr = im->clk.sccr; in get_clocks()
397 lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; in get_clocks()
410 (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT)); in get_clocks()
415 ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT)); in get_clocks()
447 qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT; in get_clocks()
[all …]
/u-boot/board/freescale/mpc8349itx/
A Dmpc8349itx.c44 im->sysconf.ddrlaw[0].ar = in fixed_sdram()
51 im->ddr.csbnds[0].csbnds = in fixed_sdram()
58 im->ddr.cs_config[1] = 0; in fixed_sdram()
59 im->ddr.cs_config[2] = 0; in fixed_sdram()
60 im->ddr.cs_config[3] = 0; in fixed_sdram()
68 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
71 im->ddr.sdram_mode = in fixed_sdram()
73 im->ddr.sdram_interval = in fixed_sdram()
80 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; in fixed_sdram()
134 volatile ddr83xx_t *ddr = &im->ddr; in dram_init()
[all …]
/u-boot/board/ve8313/
A Dve8313.c44 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
47 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); in fixed_sdram()
58 out_be32(&im->ddr.csbnds[0].csbnds, in fixed_sdram()
65 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
73 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG); in fixed_sdram()
75 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2); in fixed_sdram()
76 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); in fixed_sdram()
77 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2); in fixed_sdram()
83 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); in fixed_sdram()
97 volatile fsl_lbc_t *lbc = &im->im_lbc; in dram_init()
[all …]
/u-boot/board/ids/ids8313/
A Dids8313.c58 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
64 out_be32(&im->sysconf.ddrlaw[0].bar, in fixed_sdram()
77 out_be32(&im->ddr.cs_config[0], config); in fixed_sdram()
80 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
81 out_be32(&im->ddr.cs_config[2], 0); in fixed_sdram()
82 out_be32(&im->ddr.cs_config[3], 0); in fixed_sdram()
89 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG); in fixed_sdram()
92 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); in fixed_sdram()
128 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in dram_init() local
129 fsl_lbc_t *lbc = &im->im_lbc; in dram_init()
[all …]
/u-boot/board/freescale/mpc837xerdb/
A Dmpc837xerdb.c71 immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in dram_init() local
74 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) in dram_init()
99 immap_t *im = (immap_t *) CONFIG_SYS_IMMR; in fixed_sdram() local
106 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; in fixed_sdram()
116 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
117 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
118 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
120 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
122 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
123 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; in fixed_sdram()
[all …]
/u-boot/board/keymile/km83xx/
A Dkm83xx.c121 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in fixed_sdram() local
126 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e)); in fixed_sdram()
133 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
135 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); in fixed_sdram()
136 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); in fixed_sdram()
140 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); in fixed_sdram()
153 out_be32(&im->sysconf.ddrlaw[0].ar, in fixed_sdram()
155 out_be32(&im->ddr.csbnds[0].csbnds, in fixed_sdram()
164 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in dram_init() local
167 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) in dram_init()
[all …]
/u-boot/board/sbc8349/
A Dsbc8349.c46 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in dram_init() local
49 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) in dram_init()
97 im->ddr.csbnds[2].csbnds = in fixed_sdram()
104 im->ddr.cs_config[0] = 0; in fixed_sdram()
105 im->ddr.cs_config[1] = 0; in fixed_sdram()
106 im->ddr.cs_config[3] = 0; in fixed_sdram()
108 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
109 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
111 im->ddr.sdram_cfg = in fixed_sdram()
121 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
[all …]
/u-boot/board/freescale/mpc8323erdb/
A Dmpc8323erdb.c85 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) in dram_init()
116 im->sysconf.ddrlaw[0].ar = in fixed_sdram()
121 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
122 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
123 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
124 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
125 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
126 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; in fixed_sdram()
127 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
128 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; in fixed_sdram()
[all …]
/u-boot/board/freescale/mpc837xemds/
A Dmpc837xemds.c94 u32 rcwh = in_be32(&im->reset.rcwh); in board_eth_init()
193 u32 rcwh = in_be32(&im->reset.rcwh); in ft_tsec_fixup()
230 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) in dram_init()
266 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; in fixed_sdram()
276 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
277 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
278 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
280 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
282 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
283 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; in fixed_sdram()
[all …]
/u-boot/drivers/clk/
A Dmpc83xx_clk.h276 static inline u32 get_spmr(immap_t *im) in get_spmr() argument
278 u32 res = in_be32(&im->clk.spmr); in get_spmr()
289 static inline u32 get_sccr(immap_t *im) in get_sccr() argument
291 u32 res = in_be32(&im->clk.sccr); in get_sccr()
302 static inline u32 get_lcrr(immap_t *im) in get_lcrr() argument
304 u32 res = in_be32(&im->im_lbc.lcrr); in get_lcrr()
315 static inline u32 get_pci_sync_in(immap_t *im) in get_pci_sync_in() argument
329 static inline u32 get_csb_clk(immap_t *im) in get_csb_clk() argument
349 return (get_spmr(im) & mask) >> shift; in spmr_field()
364 return (get_sccr(im) & mask) >> shift; in sccr_field()
[all …]
A Dmpc83xx_clk.c108 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in init_single_clk() local
112 u32 csb_clk = get_csb_clk(im); in init_single_clk()
130 switch (sccr_field(im, mask)) { in init_single_clk()
153 priv->speed[clk] = csb_clk * (1 + sccr_field(im, mask)); in init_single_clk()
163 u32 pci_sync_in = get_pci_sync_in(im); in init_single_clk()
164 u32 qepmf = spmr_field(im, SPMR_CEPMF); in init_single_clk()
165 u32 qepdf = spmr_field(im, SPMR_CEPDF); in init_single_clk()
178 (1 + spmr_field(im, SPMR_LBIUCM)); in init_single_clk()
179 u32 clkdiv = lcrr_field(im, LCRR_CLKDIV); in init_single_clk()
199 u8 corepll = spmr_field(im, SPMR_COREPLL); in init_single_clk()
/u-boot/board/tqc/tqm834x/
A Dtqm834x.c63 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) in board_early_init_r()
98 im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN | in dram_init()
327 im->ddr.csbnds[cs].csbnds = 0x00000000; in set_cs_bounds()
329 im->ddr.csbnds[cs].csbnds = in set_cs_bounds()
344 im->ddr.cs_config[cs] = config; in set_cs_config()
358 im->ddr.timing_cfg_1 = in set_ddr_config()
368 im->ddr.timing_cfg_2 = in set_ddr_config()
374 im->ddr.sdram_cfg = in set_ddr_config()
380 im->ddr.sdram_mode = in set_ddr_config()
390 im->ddr.sdram_interval = in set_ddr_config()
[all …]
/u-boot/include/
A Dioports.h27 #define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20)) argument
29 #define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20)) argument
/u-boot/drivers/serial/
A Dserial_mpc8xx.c65 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; in serial_mpc8xx_setbrg() local
66 cpm8xx_t __iomem *cp = &(im->im_cpm); in serial_mpc8xx_setbrg()
83 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; in serial_mpc8xx_probe() local
86 cpm8xx_t __iomem *cp = &(im->im_cpm); in serial_mpc8xx_probe()
100 out_be32(&im->im_siu_conf.sc_sdcr, 1); in serial_mpc8xx_probe()
103 out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR); in serial_mpc8xx_probe()
106 out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR); in serial_mpc8xx_probe()
175 immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; in serial_mpc8xx_putc() local
176 cpm8xx_t __iomem *cpmp = &(im->im_cpm); in serial_mpc8xx_putc()
198 cpm8xx_t __iomem *cpmp = &(im->im_cpm); in serial_mpc8xx_getc()
[all …]
/u-boot/board/esd/vme8349/
A Dvme8349.c38 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in dram_init() local
41 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) in dram_init()
45 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; in dram_init()
98 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; in misc_init_r() local
100 clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0); in misc_init_r()

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