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Searched refs:in_be32 (Results 1 – 25 of 220) sorted by relevance

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/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dfsl_lsch2_serdes.c182 reg = in_be32(&serdes1_base->lane[i].gcr0); in setup_serdes_volt()
192 reg = in_be32(&serdes2_base->lane[i].gcr0); in setup_serdes_volt()
233 reg = in_be32(&serdes1_base->srdstcalcr); in setup_serdes_volt()
236 reg = in_be32(&serdes1_base->srdsrcalcr); in setup_serdes_volt()
242 reg = in_be32(&serdes2_base->srdstcalcr); in setup_serdes_volt()
245 reg = in_be32(&serdes2_base->srdsrcalcr); in setup_serdes_volt()
277 reg = in_be32(&serdes1_base->srdstcalcr); in setup_serdes_volt()
280 reg = in_be32(&serdes1_base->srdsrcalcr); in setup_serdes_volt()
303 reg = in_be32(&serdes2_base->srdstcalcr); in setup_serdes_volt()
306 reg = in_be32(&serdes2_base->srdsrcalcr); in setup_serdes_volt()
[all …]
/u-boot/arch/powerpc/cpu/mpc85xx/
A Dmpc8536_serdes.c116 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
123 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
128 tmp = in_be32(sd + FSL_SRDSCR2_OFFS); in fsl_serdes_init()
135 tmp = in_be32(sd + FSL_SRDSCR3_OFFS); in fsl_serdes_init()
144 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
149 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
154 tmp = in_be32(sd + FSL_SRDSCR2_OFFS); in fsl_serdes_init()
159 tmp = in_be32(sd + FSL_SRDSCR3_OFFS); in fsl_serdes_init()
166 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
173 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
[all …]
A Dqe_io.c33 in_be32(&par_io[port].cpdir2) : in qe_config_iopin()
34 in_be32(&par_io[port].cpdir1); in qe_config_iopin()
48 tmp_val = in_be32(&par_io[port].cpodr); in qe_config_iopin()
56 in_be32(&par_io[port].cppar2): in qe_config_iopin()
57 in_be32(&par_io[port].cppar1); in qe_config_iopin()
A Dfsl_corenet2_serdes.c126 u32 cfg = in_be32(&gur->rcwsr[4]); in serdes_get_first_lane()
213 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; in serdes_init()
226 sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0); in serdes_init()
233 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
268 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); in serdes_init()
277 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
285 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); in serdes_init()
295 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2); in serdes_init()
304 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
307 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2); in serdes_init()
[all …]
A Dcmd_errata.c42 if (in_be32(dcsr + offsets[i]) != 2) { in check_erratum_a4849()
63 if (in_be32(dcsr + 0x108) != x108) { in check_erratum_a4849()
101 if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) || in check_erratum_a4580()
102 (in_be32(&srds_lane->res4[1]) != 0x880000) || in check_erratum_a4580()
103 (in_be32(&srds_lane->res4[3]) != 0x40000044)) { in check_erratum_a4580()
125 if (in_be32(plldgdcr) & 0x1fe) { in check_erratum_a007212()
A Dmp.c56 (void)in_be32(&pic->pir); in cpu_reset()
99 u32 coredisrl = in_be32(&gur->coredisrl); in is_core_disabled()
125 u32 devdisr = in_be32(&gur->devdisr); in is_core_disabled()
272 whoami = in_be32(&pic->whoami); in plat_mp_up()
284 in_be32(&ccm->bstrar); in plat_mp_up()
315 in_be32(&rcpm->ctbenrl); in plat_mp_up()
345 whoami = in_be32(&pic->whoami); in plat_mp_up()
349 devdisr = in_be32(&gur->devdisr); in plat_mp_up()
358 bpcr = in_be32(&ecm->eebpcr); in plat_mp_up()
391 in_be32(&gur->devdisr); in plat_mp_up()
/u-boot/arch/powerpc/cpu/mpc8xx/
A Dimmap.c29 in_be32(&sc->sc_siumcr), in_be32(&sc->sc_sypcr)); in do_siuinfo()
32 in_be32(&sc->sc_sipend), in_be32(&sc->sc_simask)); in do_siuinfo()
34 in_be32(&sc->sc_siel), in_be32(&sc->sc_sivec)); in do_siuinfo()
36 in_be32(&sc->sc_tesr), in_be32(&sc->sc_sdcr)); in do_siuinfo()
51 i, in_be32(p), i, in_be32(p + 1)); in do_memcinfo()
56 in_be32(&memctl->memc_mamr), in_be32(&memctl->memc_mbmr)); in do_memcinfo()
143 binary("PB_DIR", in_be32(R++), PB_NBITS); in do_iopinfo()
145 binary("PB_PAR", in_be32(R++), PB_NBITS); in do_iopinfo()
147 binary("PB_ODR", in_be32(R++), PB_NB_ODR); in do_iopinfo()
149 binary("PB_DAT", in_be32(R++), PB_NBITS); in do_iopinfo()
[all …]
A Dcpu.c50 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff; in checkicache()
91 u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff; in checkdcache()
160 if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678) in check_CPU()
247 if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS) in get_tbclk()
250 pll = in_be32(&immap->im_clkrst.car_plprcr); in get_tbclk()
270 if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 || in get_tbclk()
/u-boot/arch/m68k/cpu/mcf5445x/
A Dspeed.c67 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) in clock_exit_limp()
94 temp = in_be32(&pll->pcr); in setup_5441x_clocks()
99 temp = in_be32(&pll->pdr); in setup_5441x_clocks()
108 vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) * in setup_5441x_clocks()
114 pdr = in_be32(&pll->pdr); in setup_5441x_clocks()
175 pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF; in setup_5445x_clocks()
190 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000; in setup_5445x_clocks()
206 j = (in_be32(&pll->pcr) & 0xFF000000) >> 24; in setup_5445x_clocks()
217 pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF; in setup_5445x_clocks()
229 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); in setup_5445x_clocks()
[all …]
/u-boot/arch/powerpc/cpu/mpc83xx/
A Dserdes.c56 tmp = in_be32(regs + FSL_SRDSCR0_OFFS); in fsl_setup_serdes()
61 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
70 tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); in fsl_setup_serdes()
83 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
88 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
106 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
111 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
128 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
133 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
150 tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); in fsl_setup_serdes()
A Dqe_io.c47 in_be32(&par_io->ioport[port].dir2) : in qe_cfg_iopin()
48 in_be32(&par_io->ioport[port].dir1); in qe_cfg_iopin()
62 tmp_val = in_be32(&par_io->ioport[port].podr); in qe_cfg_iopin()
70 in_be32(&par_io->ioport[port].ppar2) : in qe_cfg_iopin()
71 in_be32(&par_io->ioport[port].ppar1); in qe_cfg_iopin()
/u-boot/drivers/net/fm/
A Dtgec_phy.c32 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_write()
43 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_write()
50 while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY) in tgec_mdio_write()
74 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_read()
85 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_read()
93 while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY) in tgec_mdio_read()
97 if (in_be32(&regs->mdio_stat) & MDIO_STAT_RD_ER) in tgec_mdio_read()
100 return in_be32(&regs->mdio_data) & 0xffff; in tgec_mdio_read()
/u-boot/drivers/ddr/fsl/
A Dmpc85xx_ddr_gen3.c220 save1 = in_be32(&ddr->debug[12]); in fsl_ddr_set_memctl_regs()
221 save2 = in_be32(&ddr->debug[21]); in fsl_ddr_set_memctl_regs()
228 while (!(in_be32(&ddr->debug[1]) & 0x2)) in fsl_ddr_set_memctl_regs()
370 val32 = in_be32(&ddr->debug[18]) | 0x2; in fsl_ddr_set_memctl_regs()
379 val32 = in_be32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
401 && in_be32(&ddr->sdram_cfg) & 0x80000) { in fsl_ddr_set_memctl_regs()
420 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
506 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
515 in_be32(&ddr->timing_cfg_2)); in fsl_ddr_set_memctl_regs()
530 while (in_be32(&ddr->debug[1]) & 0x800) in fsl_ddr_set_memctl_regs()
[all …]
/u-boot/arch/m68k/cpu/mcf5227x/
A Dspeed.c65 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) in clock_exit_limp()
80 pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF; in get_clocks()
92 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
95 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); in get_clocks()
99 ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * in get_clocks()
105 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
114 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1; in get_clocks()
117 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; in get_clocks()
/u-boot/board/xes/common/
A Dfsl_8xxx_pci.c30 u32 devdisr = in_be32(&gur->devdisr); in pci_init_board()
31 uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD; in pci_init_board()
32 uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32; in pci_init_board()
33 uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB; in pci_init_board()
34 uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1; in pci_init_board()
A Dfsl_8xxx_clk.c21 if (in_be32(&gur->gpporcr) & 0x10000) in get_board_sys_clk()
39 u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9; in get_board_ddr_clk()
45 if (in_be32(&gur->gpporcr) & 0x20000) in get_board_ddr_clk()
/u-boot/arch/powerpc/cpu/mpc8xxx/
A Dlaw.c39 ((u64)in_be32(LAWBARH_ADDR(idx)) << 32) | in get_law_base_addr()
40 in_be32(LAWBARL_ADDR(idx)); in get_law_base_addr()
65 in_be32(LAWAR_ADDR(idx)); in set_law()
76 in_be32(LAWAR_ADDR(idx)); in disable_law()
87 lawar = in_be32(LAWAR_ADDR(i)); in get_law_entry()
166 lawar = in_be32(LAWAR_ADDR(i)); in print_laws()
169 i, in_be32(LAWBARH_ADDR(i)), in print_laws()
170 i, in_be32(LAWBARL_ADDR(i))); in print_laws()
231 u32 lawar = in_be32(LAWAR_ADDR(i)); in disable_non_ddr_laws()
286 u32 lawar = in_be32(LAWAR_ADDR(i)); in init_laws()
[all …]
A Dsrio.c85 conf_lane = (in_be32((void *)&srds_regs->srdspccr0) in srio_erratum_a004034()
87 init_lane = (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
95 if (in_be32((void *)&srds_regs->bank[0].rstctl) in srio_erratum_a004034()
106 if (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
158 in_be32(&srds_regs->lane[idx].gcr0); in srio_erratum_a004034()
175 in_be32(&srds_regs->lane[idx].gcr0); in srio_erratum_a004034()
195 (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
197 if (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
216 if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr) in srio_erratum_a004034()
413 while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT in srio_boot_master_release_slave()
[all …]
/u-boot/arch/m68k/cpu/mcf532x/
A Dspeed.c69 u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; in get_sys_clock()
70 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); in get_sys_clock()
71 u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1; in get_sys_clock()
155 u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1; in clock_pll()
156 mfd = (in_be32(&pll->pcr) & 0x3F) + 1; in clock_pll()
201 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) in clock_pll()
234 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) in clock_pll()
/u-boot/board/freescale/t102xrdb/
A Dt102xrdb.c55 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in checkboard()
106 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & in board_mux_lane()
236 u32 val = in_be32(&pgpio->gpdat); in board_mmc_getcd()
247 u32 val = in_be32(&pgpio->gpdat); in board_mmc_getwp()
275 val = in_be32(&pgpio->gpdat); in t1023rdb_ctrl()
281 val = in_be32(&pgpio->gpdat); in t1023rdb_ctrl()
289 val = in_be32(&pgpio->gpdat); in t1023rdb_ctrl()
324 val = in_be32(&pgpio->gpdat); in t1023rdb_ctrl()
330 val = in_be32(&pgpio->gpdat); in t1023rdb_ctrl()
338 val = in_be32(&pgpio->gpdat); in t1023rdb_ctrl()
/u-boot/board/Arcturus/ucp1020/
A Dspl.c45 setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); in board_init_f()
47 in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); in board_init_f()
50 in_be32(&gur->pmuxcr); in board_init_f()
57 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; in board_init_f()
/u-boot/board/freescale/p1_p2_rdb_pc/
A Dspl.c37 setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); in board_init_f()
39 in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); in board_init_f()
42 in_be32(&gur->pmuxcr); in board_init_f()
49 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; in board_init_f()
/u-boot/board/freescale/common/
A Dmpc85xx_sleep.c29 if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR) in is_warm_boot()
52 src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8); in dp_ddr_restore()
91 start_addr = in_be32(&scfg->sparecr[1]); in fsl_dp_resume()
/u-boot/arch/powerpc/include/asm/
A Dmpc85xx_gpio.h30 dir |= (in_be32(&gpio->gpdir) & ~mask); in mpc85xx_gpio_set()
31 val |= (in_be32(&gpio->gpdat) & ~mask); in mpc85xx_gpio_set()
62 return in_be32(&gpio->gpdat) & mask; in mpc85xx_gpio_get()
/u-boot/arch/arm/cpu/armv7/ls102xa/
A Dclock.c51 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> in get_sys_info()
53 sys_info->freq_ddrbus *= (in_be32(&gur->rcwsr[0]) >> in get_sys_info()
57 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; in get_sys_info()
65 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) in get_sys_info()

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