Searched refs:init_val (Results 1 – 4 of 4) sorted by relevance
| /u-boot/drivers/ddr/marvell/a38x/ |
| A D | ddr3_training_pbs.c | 46 int init_val = (search_dir == HWS_LOW2HIGH) ? 0 : iterations; in ddr3_tip_pbs() local
82 tm->if_act_mask, init_val, iterations, in ddr3_tip_pbs()
212 tm->if_act_mask, init_val, in ddr3_tip_pbs()
390 init_val = 0; in ddr3_tip_pbs()
395 search_dir, dir, tm->if_act_mask, init_val, in ddr3_tip_pbs()
476 init_val = (search_dir == HWS_LOW2HIGH) ? 0 : iterations; in ddr3_tip_pbs()
523 init_val, iterations, in ddr3_tip_pbs()
615 init_val = (pbs_mode == PBS_RX_MODE) ? 0 : iterations; in ddr3_tip_pbs()
622 init_val, iterations, pbs_pattern, in ddr3_tip_pbs()
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| /u-boot/drivers/video/nexell/soc/ |
| A D | s5pxx18_soc_disptop.c | 138 void nx_disp_top_set_hdmifield(u32 enable, u32 init_val, u32 vsynctoggle, in nx_disp_top_set_hdmifield() argument
146 regvalue = ((enable & 0x01) << 0) | ((init_val & 0x01) << 1) | in nx_disp_top_set_hdmifield()
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| A D | s5pxx18_soc_disptop.h | 364 void nx_disp_top_set_hdmifield(u32 enable, u32 init_val, u32 vsynctoggle,
381 void nx_disp_top_set_hdmifield(u32 enable, u32 init_val, u32 vsynctoggle,
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| /u-boot/cmd/ |
| A D | nvedit.c | 633 char *init_val; in do_env_edit() local
643 init_val = env_get(argv[1]); in do_env_edit()
644 if (init_val) in do_env_edit()
645 snprintf(buffer, CONFIG_SYS_CBSIZE, "%s", init_val); in do_env_edit()
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