Searched refs:instruction (Results 1 – 25 of 45) sorted by relevance
12
30 undefined instruction38 undefined instruction46 undefined instruction51 undefined instruction60 Illegal instruction
53 - This instruction does nothing62 - i.MX28-specific instruction!67 - i.MX28-specific instruction!140 - This instruction does nothing.152 T -- TAG instruction153 N -- NOOP instruction154 L -- LOAD instruction155 F -- FILL instruction156 J -- JUMP instruction157 C -- CALL instruction[all …]
12 AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to16 - Intermixable 32-bit and 16-bit instruction sets without the need for19 - RISC-style register-based instruction set.34 - Three instruction extension space for application acceleration:50 - 16-/32-bit mixable instruction format.
19 The ColdFire instruction set is "assembly source" compatible but an evolution20 of the original 68000 instruction set. Some not much used instructions has
16 - icache-line-size: Contains instruction line size.18 - icache-size: Contains instruction cache size.23 - altr,has-initda: Specifies CPU support initda instruction, should be 1.
7 When the CPU detects an instruction that it cannot execute it raises an50 instruction. The exception syndrome register ESR register contains information52 instruction led to the exception.59 code of the instructions preceding the crash and in parentheses the instruction78 10:* e7f7defb .inst 0xe7f7defb ; undefined <-- trapping instruction80 Code starting with the faulting instruction
23 Do not enable instruction cache in U-Boot.30 Do not enable instruction cache in SPL.
1 Core instruction prefetch disable3 To disable instruction prefetch of core; hwconfig needs to be updated.
136 static void hd44780_instruction(unsigned long instruction) in hd44780_instruction() argument141 max6957aax_write(MAX6957AAX_HD44780_DATA, instruction); in hd44780_instruction()144 if (instruction == HD44780_CLEAR_DISPLAY) in hd44780_instruction()
586 - turn on the instruction cache587 - unlock the entire instruction cache588 - invalidate the instruction cache589 - lock a branch instruction in the instruction cache591 - jump to the branch instruction596 - turn on the instruction cache597 - unlock the entire instruction cache598 - invalidate the instruction cache599 - jump to a branch instruction602 - invalidate the instruction cache[all …]
31 if it is an illegal instruction, privileged instruction or
15 While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile
50 bool "Enable instruction cache"56 bool "Lock instruction cache"62 bool "Flash invalidate instruction cache"68 bool "Enable m bit on bus for instruction fetches"131 bool "Enable instruction cache"137 bool "Lock instruction cache"143 bool "Flash invalidate instruction cache"149 bool "Enable m bit on bus for instruction fetches"
32 Do not enable instruction cache in U-Boot.39 Do not enable instruction cache in SPL.76 Choose this option to target the RV32I base integer instruction set.83 Choose this option to target the RV64I base integer instruction set.263 old specification will result in an illegal instruction
4 with a different purpose, a little like a simple instruction set.
293 unsigned int instruction; in smi_sector_erase() local313 instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE; in smi_sector_erase()329 writel(instruction, &smicntl->smi_tr); in smi_sector_erase()
105 echo Code starting with the faulting instruction > $T.aa
54 without resorting to software trapping and/or instruction set
57 If an illegal instruction or an illegal memory access occurs, the
115 Do not enable instruction cache in U-Boot.122 Do not enable instruction cache in SPL.
70 these instruction will produce the same effect:
1 This document describes the instruction to build and flash ATF/OPTEE/U-Boot on
149 to "SPI Little Endian Boot mode" as per instruction at169 to "ARM NAND Boot mode" as per instruction at189 1. Set the SW3 dip switch to "ARM MMC Boot mode" as per instruction at
34 - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1113 - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
Completed in 32 milliseconds