| /u-boot/arch/microblaze/cpu/ |
| A D | interrupts.c | 55 mask = intc->ier; in enable_one_interrupt()
59 intc->ier); in enable_one_interrupt()
61 intc->iar, intc->mer); in enable_one_interrupt()
70 mask = intc->ier; in disable_one_interrupt()
76 intc->iar, intc->mer); in disable_one_interrupt()
107 intc->mer = 0; in intc_init()
108 intc->ier = 0; in intc_init()
111 intc->mer = 0x3; in intc_init()
114 intc->iar, intc->mer); in intc_init()
170 intc->iar, intc->mer); in interrupt_handler()
[all …]
|
| /u-boot/arch/arm/dts/ |
| A D | zynq-7000.dtsi | 51 interrupt-parent = <&intc>;
103 interrupt-parent = <&intc>;
110 interrupt-parent = <&intc>;
121 interrupt-parent = <&intc>;
133 interrupt-parent = <&intc>;
145 interrupt-parent = <&intc>;
154 interrupt-parent = <&intc>;
165 interrupt-parent = <&intc>;
217 interrupt-parent = <&intc>;
229 interrupt-parent = <&intc>;
[all …]
|
| A D | da850-lego-ev3.dts | 38 intc: interrupt-controller@fffee000 { label
39 compatible = "ti,cp-intc";
42 ti,intc-size = <101>;
53 interrupt-parent = <&intc>;
|
| A D | omap3-evm-common.dtsi | 61 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
62 interrupt-parent = <&intc>;
118 interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
125 interrupts-extended = <&intc 86 &omap3_pmx_core 0x12e>;
|
| A D | zynq-cse-qspi.dtsi | 40 interrupt-parent = <&intc>;
43 intc: interrupt-controller@f8f01000 { label
56 interrupt-parent = <&intc>;
|
| A D | bcm2836.dtsi | 13 compatible = "brcm,bcm2836-l1-intc";
75 &intc {
|
| A D | bcm2837.dtsi | 12 compatible = "brcm,bcm2836-l1-intc";
78 &intc {
|
| A D | imx6qdl-mba6a.dtsi | 9 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
|
| A D | logicpd-torpedo-som.dtsi | 78 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
79 interrupt-parent = <&intc>;
172 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
|
| A D | kirkwood-98dx4122.dtsi | 30 interrupt-map = <0 0 0 0 &intc 9>;
|
| A D | logicpd-som-lv.dtsi | 83 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
84 interrupt-parent = <&intc>;
128 interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
284 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
|
| A D | r8a7792-blanche.dts | 208 intc {
210 function = "intc";
240 function = "intc";
|
| A D | omap3-evm-processor-common.dtsi | 180 interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
184 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
188 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
|
| /u-boot/arch/mips/dts/ |
| A D | jz4780.dtsi | 17 intc: interrupt-controller@10001000 { label
18 compatible = "ingenic,jz4780-intc";
74 interrupt-parent = <&intc>;
88 interrupt-parent = <&intc>;
102 interrupt-parent = <&intc>;
116 interrupt-parent = <&intc>;
130 interrupt-parent = <&intc>;
|
| A D | mt7628a.dtsi | 232 interrupt-parent = <&intc>;
236 intc: interrupt-controller@200 { label
237 compatible = "ralink,rt2880-intc";
244 reset-names = "intc";
249 ralink,intc-registers = <0x9c 0xa0
269 interrupt-parent = <&intc>;
319 interrupt-parent = <&intc>;
337 interrupt-parent = <&intc>;
355 interrupt-parent = <&intc>;
395 interrupt-parent = <&intc>;
|
| A D | mscc,servalt.dtsi | 58 interrupt-parent = <&intc>;
65 intc: interrupt-controller@70 { label
|
| /u-boot/arch/nds32/dts/ |
| A D | ag101p.dts | 6 interrupt-parent = <&intc>;
36 intc: interrupt-controller { label
|
| A D | ae3xx.dts | 6 interrupt-parent = <&intc>;
43 intc: interrupt-controller { label
|
| /u-boot/arch/riscv/dts/ |
| A D | fu540-c000.dtsi | 36 compatible = "riscv,cpu-intc";
60 compatible = "riscv,cpu-intc";
84 compatible = "riscv,cpu-intc";
108 compatible = "riscv,cpu-intc";
132 compatible = "riscv,cpu-intc";
|
| A D | ae350_32.dts | 41 compatible = "riscv,cpu-intc";
62 compatible = "riscv,cpu-intc";
83 compatible = "riscv,cpu-intc";
104 compatible = "riscv,cpu-intc";
|
| A D | ae350_64.dts | 41 compatible = "riscv,cpu-intc";
62 compatible = "riscv,cpu-intc";
83 compatible = "riscv,cpu-intc";
104 compatible = "riscv,cpu-intc";
|
| A D | microchip-mpfs-icicle-kit.dts | 47 compatible = "riscv,cpu-intc";
78 compatible = "riscv,cpu-intc";
109 compatible = "riscv,cpu-intc";
140 compatible = "riscv,cpu-intc";
171 compatible = "riscv,cpu-intc";
|
| /u-boot/doc/device-tree-bindings/i2c/ |
| A D | i2c-cdns.txt | 18 interrupt-parent = <&intc>;
|
| /u-boot/doc/device-tree-bindings/spi/ |
| A D | spi-zynq-qspi.txt | 22 interrupt-parent = <&intc>;
|
| A D | spi-zynq.txt | 27 interrupt-parent = <&intc>;
|