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Searched refs:lane_cnt (Results 1 – 3 of 3) sorted by relevance

/u-boot/board/gdsys/common/
A Ddp501.c56 u8 lane_cnt; in dp501_link_training() local
70 lane_cnt = 4; in dp501_link_training()
72 lane_cnt = max_lane_cnt; in dp501_link_training()
73 if (lane_cnt != max_lane_cnt) in dp501_link_training()
75 max_lane_cnt, lane_cnt); in dp501_link_training()
76 i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */ in dp501_link_training()
/u-boot/drivers/video/exynos/
A Dexynos_dp.c179 unsigned char lane_cnt[16]; in exynos_dp_handle_edid() local
183 memset(lane_cnt, 0, 16); in exynos_dp_handle_edid()
232 priv->lane_cnt = temp; in exynos_dp_handle_edid()
288 buf[1] = priv->lane_cnt; in exynos_dp_link_start()
297 priv->lane_cnt); in exynos_dp_link_start()
405 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_read_dpcd_lane_stat()
511 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_process_clock_recovery()
546 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_process_clock_recovery()
630 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_process_equalizer_training()
679 for (i = 0; i < priv->lane_cnt; i++) in exynos_dp_process_equalizer_training()
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/u-boot/arch/arm/mach-exynos/include/mach/
A Ddp_info.h70 unsigned char lane_cnt; member

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