Home
last modified time | relevance | path

Searched refs:layout (Results 1 – 25 of 107) sorted by relevance

12345

/u-boot/common/eeprom/
A Deeprom_layout.c40 layout->fields = layout_unknown; in __eeprom_layout_assign()
53 struct eeprom_field *fields = layout->fields; in eeprom_layout_print()
55 for (i = 0; i < layout->num_of_fields; i++) in eeprom_layout_print()
71 struct eeprom_field *fields = layout->fields; in eeprom_layout_update_field()
79 for (i = 0; i < layout->num_of_fields; i++) { in eeprom_layout_update_field()
112 layout->layout_version = layout_version; in eeprom_layout_setup()
115 layout->data = buf; in eeprom_layout_setup()
117 layout->fields[i].buf = buf; in eeprom_layout_setup()
118 buf += layout->fields[i].size; in eeprom_layout_setup()
121 layout->data_size = buf_size; in eeprom_layout_setup()
[all …]
/u-boot/drivers/clk/at91/
A Dclk-generic.c28 const struct clk_pcr_layout *layout; member
42 (gck->id & gck->layout->pid_mask)); in clk_gck_enable()
44 gck->layout->cmd | AT91_PMC_PCR_GCKEN, in clk_gck_enable()
55 (gck->id & gck->layout->pid_mask)); in clk_gck_disable()
58 gck->layout->cmd); in clk_gck_disable()
79 (gck->id & gck->layout->pid_mask)); in clk_gck_set_parent()
81 gck->layout->gckcss_mask | gck->layout->cmd, in clk_gck_set_parent()
83 gck->layout->cmd); in clk_gck_set_parent()
105 (gck->id & gck->layout->pid_mask)); in clk_gck_set_rate()
109 gck->layout->cmd); in clk_gck_set_rate()
[all …]
A Dclk-programmable.c42 const struct clk_programmable_layout *layout = prog->layout; in clk_programmable_get_rate() local
48 if (layout->is_pres_direct) in clk_programmable_get_rate()
59 const struct clk_programmable_layout *layout = prog->layout; in clk_programmable_set_parent() local
73 if (layout->have_slck_mck) in clk_programmable_set_parent()
76 if (index > layout->css_mask) { in clk_programmable_set_parent()
91 const struct clk_programmable_layout *layout = prog->layout; in clk_programmable_set_rate() local
99 if (layout->is_pres_direct) { in clk_programmable_set_rate()
102 if (shift > layout->pres_mask) in clk_programmable_set_rate()
115 layout->pres_mask << layout->pres_shift, in clk_programmable_set_rate()
118 if (layout->is_pres_direct) in clk_programmable_set_rate()
[all …]
A Dclk-peripheral.c38 const struct clk_pcr_layout *layout; member
131 (periph->id & periph->layout->pid_mask)); in clk_sam9x5_peripheral_enable()
133 periph->layout->cmd | AT91_PMC_PCR_EN, in clk_sam9x5_peripheral_enable()
134 periph->layout->cmd | AT91_PMC_PCR_EN); in clk_sam9x5_peripheral_enable()
147 (periph->id & periph->layout->pid_mask)); in clk_sam9x5_peripheral_disable()
149 AT91_PMC_PCR_EN | periph->layout->cmd, in clk_sam9x5_peripheral_disable()
150 periph->layout->cmd); in clk_sam9x5_peripheral_disable()
201 periph->layout->div_mask | periph->layout->cmd, in clk_sam9x5_peripheral_set_rate()
203 periph->layout->cmd); in clk_sam9x5_peripheral_set_rate()
217 const struct clk_pcr_layout *layout, in at91_clk_register_sam9x5_peripheral() argument
[all …]
A Dclk-sam9x60-pll.c115 cmul = (val & pll->layout->mul_mask) >> pll->layout->mul_shift; in sam9x60_frac_pll_set_rate()
116 cfrac = (val & pll->layout->frac_mask) >> pll->layout->frac_shift; in sam9x60_frac_pll_set_rate()
153 mul = (val & pll->layout->mul_mask) >> pll->layout->mul_shift; in sam9x60_frac_pll_get_rate()
154 frac = (val & pll->layout->frac_mask) >> pll->layout->frac_shift; in sam9x60_frac_pll_get_rate()
269 pll->layout->endiv_mask, in sam9x60_div_pll_enable()
323 if (div == ((val & pll->layout->div_mask) >> pll->layout->div_shift)) in sam9x60_div_pll_set_rate()
328 pll->layout->div_mask, in sam9x60_div_pll_set_rate()
359 div = (val & pll->layout->div_mask) >> pll->layout->div_shift; in sam9x60_div_pll_get_rate()
391 pll->layout = layout; in sam9x60_clk_register_pll()
413 characteristics, layout, in sam9x60_clk_register_div_pll()
[all …]
A Dclk-master.c43 const struct clk_master_layout *layout; member
79 const struct clk_master_layout *layout = master->layout; in clk_master_get_rate() local
89 pmc_read(master->base, master->layout->offset, &mckr); in clk_master_get_rate()
90 mckr &= layout->mask; in clk_master_get_rate()
92 pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK; in clk_master_get_rate()
117 int num_parents, const struct clk_master_layout *layout, in at91_clk_register_master() argument
127 !layout || !characteristics || !mux_table) in at91_clk_register_master()
134 master->layout = layout; in at91_clk_register_master()
140 pmc_read(master->base, master->layout->offset, &val); in at91_clk_register_master()
A Dpmc.h93 const struct clk_pll_layout *layout, bool critical);
98 const struct clk_pll_layout *layout, bool critical);
102 const struct clk_master_layout *layout,
119 const struct clk_programmable_layout *layout,
129 const struct clk_pcr_layout *layout,
134 const struct clk_pcr_layout *layout, const char *name,
/u-boot/drivers/mtd/nand/raw/
A Dnand_bch.c116 struct nand_ecclayout *layout = nand->ecc.layout; in nand_bch_init() local
154 if (!layout) { in nand_bch_init()
163 layout = &nbc->ecclayout; in nand_bch_init()
164 layout->eccbytes = eccsteps*eccbytes; in nand_bch_init()
167 if (layout->eccbytes+2 > mtd->oobsize) { in nand_bch_init()
174 for (i = 0; i < layout->eccbytes; i++) in nand_bch_init()
175 layout->eccpos[i] = mtd->oobsize-layout->eccbytes+i; in nand_bch_init()
177 layout->oobfree[0].offset = 2; in nand_bch_init()
178 layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes; in nand_bch_init()
180 nand->ecc.layout = layout; in nand_bch_init()
[all …]
A Ddavinci_nand.c375 saved_ecc_layout = chip->ecc.layout; in nand_davinci_write_page()
377 mtd->oobavail = chip->ecc.layout->oobavail; in nand_davinci_write_page()
406 chip->ecc.layout = saved_ecc_layout; in nand_davinci_write_page()
438 mtd->oobavail = chip->ecc.layout->oobavail; in nand_davinci_read_page_hwecc()
441 eccpos = chip->ecc.layout->eccpos; in nand_davinci_read_page_hwecc()
467 chip->ecc.layout = saved_ecc_layout; in nand_davinci_read_page_hwecc()
739 struct nand_ecclayout *layout; in davinci_nand_init() local
742 layout->oobavail = 0; in davinci_nand_init()
743 for (i = 0; i < ARRAY_SIZE(layout->oobfree) && in davinci_nand_init()
744 layout->oobfree[i].length; i++) in davinci_nand_init()
[all …]
A Dsunxi_nand.c227 struct nand_ecclayout layout; member
1398 struct nand_ecclayout *layout; in sunxi_nand_hw_common_ecc_ctrl_init() local
1442 layout = &data->layout; in sunxi_nand_hw_common_ecc_ctrl_init()
1452 ecc->layout = layout; in sunxi_nand_hw_common_ecc_ctrl_init()
1486 layout = ecc->layout; in sunxi_nand_hw_ecc_ctrl_init()
1491 layout->oobfree[i].offset = in sunxi_nand_hw_ecc_ctrl_init()
1540 layout = ecc->layout; in sunxi_nand_hw_syndrome_ecc_ctrl_init()
1544 layout->eccpos[i] = i; in sunxi_nand_hw_syndrome_ecc_ctrl_init()
1561 kfree(ecc->layout); in sunxi_nand_ecc_cleanup()
1595 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL); in sunxi_nand_ecc_init()
[all …]
A Dfsmc_nand.c419 nand->ecc.layout = &fsmc_ecc1_layout; in fsmc_nand_switch_ecc()
429 nand->ecc.layout = NULL; in fsmc_nand_switch_ecc()
490 nand->ecc.layout = &fsmc_ecc4_sp_layout; in fsmc_nand_init()
493 nand->ecc.layout = &fsmc_ecc4_224_layout; in fsmc_nand_init()
495 nand->ecc.layout = &fsmc_ecc4_lp_layout; in fsmc_nand_init()
502 nand->ecc.layout = &fsmc_ecc1_layout; in fsmc_nand_init()
/u-boot/drivers/dfu/
A Ddfu_mmc.c105 switch (dfu->layout) { in mmc_file_op()
202 switch (dfu->layout) { in dfu_write_medium_mmc()
228 switch (dfu->layout) { in dfu_flush_medium_mmc()
252 switch (dfu->layout) { in dfu_get_medium_size_mmc()
303 switch (dfu->layout) { in dfu_read_medium_mmc()
383 dfu->layout = DFU_RAW_ADDR; in dfu_fill_entity_mmc()
418 dfu->layout = DFU_RAW_ADDR; in dfu_fill_entity_mmc()
423 dfu->layout = DFU_FS_FAT; in dfu_fill_entity_mmc()
425 dfu->layout = DFU_FS_EXT4; in dfu_fill_entity_mmc()
427 dfu->layout = DFU_SKIP; in dfu_fill_entity_mmc()
[all …]
A Ddfu_ram.c20 if (dfu->layout != DFU_RAM_ADDR) { in dfu_transfer_medium_ram()
21 pr_err("unsupported layout: %s\n", dfu_get_layout(dfu->layout)); in dfu_transfer_medium_ram()
76 dfu->layout = DFU_RAM_ADDR; in dfu_fill_entity_ram()
A Ddfu_nand.c110 switch (dfu->layout) { in dfu_write_medium_nand()
116 dfu_get_layout(dfu->layout)); in dfu_write_medium_nand()
134 switch (dfu->layout) { in dfu_read_medium_nand()
140 dfu_get_layout(dfu->layout)); in dfu_read_medium_nand()
206 dfu->layout = DFU_RAW_ADDR; in dfu_fill_entity_nand()
216 dfu->layout = DFU_RAW_ADDR; in dfu_fill_entity_nand()
A Ddfu_mtd.c171 switch (dfu->layout) { in dfu_read_medium_mtd()
177 dfu_get_layout(dfu->layout)); in dfu_read_medium_mtd()
188 switch (dfu->layout) { in dfu_write_medium_mtd()
194 dfu_get_layout(dfu->layout)); in dfu_write_medium_mtd()
271 dfu->layout = DFU_RAW_ADDR; in dfu_fill_entity_mtd()
281 dfu->layout = DFU_RAW_ADDR; in dfu_fill_entity_mtd()
/u-boot/board/compulab/common/
A Deeprom.c473 void eeprom_layout_assign(struct eeprom_layout *layout, int layout_version) in eeprom_layout_assign() argument
475 switch (layout->layout_version) { in eeprom_layout_assign()
477 layout->fields = layout_legacy; in eeprom_layout_assign()
478 layout->num_of_fields = ARRAY_SIZE(layout_legacy); in eeprom_layout_assign()
481 layout->fields = layout_v1; in eeprom_layout_assign()
482 layout->num_of_fields = ARRAY_SIZE(layout_v1); in eeprom_layout_assign()
485 layout->fields = layout_v2; in eeprom_layout_assign()
486 layout->num_of_fields = ARRAY_SIZE(layout_v2); in eeprom_layout_assign()
489 layout->fields = layout_v3; in eeprom_layout_assign()
490 layout->num_of_fields = ARRAY_SIZE(layout_v3); in eeprom_layout_assign()
[all …]
/u-boot/doc/
A DREADME.bcmns31 BCMNS3 QSPI memory layout
8 Following is the QSPI flash memory layout.
10 /* QSPI layout
/u-boot/include/
A Deeprom_layout.h27 void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf,
29 __weak void __eeprom_layout_assign(struct eeprom_layout *layout,
/u-boot/doc/usage/
A Dmbr.rst18 partition layout based on the provided text description. The partition
19 layout is alternatively read from the 'mbr_parts' environment variable.
21 proper partition layout.
52 To check if the layout on the MMC #0 storage device matches the provided
65 echo MBR layout needs to be updated
71 The 'mbr verify' returns 0 if the layout matches the one on the storage
A Ddfu.rst292 dev: eMMC alt: 0 name: spl layout: RAW_ADDR
293 dev: eMMC alt: 1 name: u-boot layout: RAW_ADDR
344 dev: SF alt: 0 name: spl layout: RAW_ADDR
345 dev: SF alt: 1 name: ssbl layout: RAW_ADDR
347 dev: NAND alt: 3 name: UBI layout: RAW_ADDR
377 dev: MTD alt: 0 name: spl layout: RAW_ADDR
378 dev: MTD alt: 1 name: u-boot layout: RAW_ADDR
380 dev: MTD alt: 3 name: UBI layout: RAW_ADDR
402 dev: eMMC alt: 0 name: sdcard layout: RAW_ADDR
403 dev: VIRT alt: 1 name: otp layout: RAW_ADDR
[all …]
/u-boot/cmd/
A Deeprom.c314 struct eeprom_layout layout; in eeprom_execute_command() local
342 eeprom_layout_setup(&layout, eeprom_buf, CONFIG_SYS_EEPROM_SIZE, in eeprom_execute_command()
346 layout.print(&layout); in eeprom_execute_command()
350 layout.update(&layout, key, value); in eeprom_execute_command()
352 rcode = eeprom_write(i2c_addr, 0, layout.data, CONFIG_SYS_EEPROM_SIZE); in eeprom_execute_command()
/u-boot/doc/board/st/
A Dstm32mp1.rst524 dev: RAM alt: 0 name: uImage layout: RAM_ADDR
527 dev: eMMC alt: 3 name: mmc0_fsbl1 layout: RAW_ADDR
528 dev: eMMC alt: 4 name: mmc0_fsbl2 layout: RAW_ADDR
529 dev: eMMC alt: 5 name: mmc0_ssbl layout: RAW_ADDR
530 dev: eMMC alt: 6 name: mmc0_bootfs layout: RAW_ADDR
532 dev: eMMC alt: 8 name: mmc0_rootfs layout: RAW_ADDR
536 dev: eMMC alt: 12 name: mmc1_ssbl layout: RAW_ADDR
541 dev: MTD alt: 17 name: nor0 layout: RAW_ADDR
542 dev: MTD alt: 18 name: nand0 layout: RAW_ADDR
543 dev: VIRT alt: 19 name: OTP layout: RAW_ADDR
[all …]
/u-boot/include/fsl-mc/
A Dfsl_dpni.h140 #define DPNI_CMD_SET_BUFFER_LAYOUT(cmd, layout, queue) \ argument
143 MC_CMD_OP(cmd, 1, 0, 16, uint16_t, layout->private_data_size); \
144 MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_align); \
145 MC_CMD_OP(cmd, 0, 32, 16, uint16_t, layout->options); \
146 MC_CMD_OP(cmd, 0, 48, 1, int, layout->pass_timestamp); \
147 MC_CMD_OP(cmd, 0, 49, 1, int, layout->pass_parser_result); \
148 MC_CMD_OP(cmd, 0, 50, 1, int, layout->pass_frame_status); \
149 MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_head_room); \
150 MC_CMD_OP(cmd, 1, 48, 16, uint16_t, layout->data_tail_room); \
805 const struct dpni_buffer_layout *layout,
[all …]
/u-boot/drivers/mtd/nand/raw/brcmnand/
A Dbrcmnand.c904 struct nand_ecclayout *layout; in brcmnand_create_layout() local
911 layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL); in brcmnand_create_layout()
913 layout = devm_kzalloc(host->pdev, sizeof(*layout), GFP_KERNEL); in brcmnand_create_layout()
915 if (!layout) in brcmnand_create_layout()
948 return layout; in brcmnand_create_layout()
965 layout->eccbytes = req * sectors; in brcmnand_create_layout()
1000 return layout; in brcmnand_create_layout()
1006 struct nand_ecclayout *layout; in brcmstb_choose_ecc_layout() local
1014 if (!layout) { in brcmstb_choose_ecc_layout()
1020 return layout; in brcmstb_choose_ecc_layout()
[all …]
/u-boot/arch/x86/include/asm/arch-apollolake/acpi/
A Dglobalnvs.asl8 * NOTE: The layout of the GNVS structure below must match the layout in

Completed in 174 milliseconds

12345